RA6M3

Detailed Description

Build Time Configurations for ra6m3_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
SDRAM
SDRAM > Timings
tRAS (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles	6 cycles	Row Active Interval
tRCD (cycles)	1 cycles 2 cycles 3 cycles 4 cycles	3 cycles	Row Column Latency
tRP (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles	3 cycles	Row Precharge Interval
tWR (cycles)	1 cycles 2 cycles	2 cycles	Write Recovery Interval
tCL (cycles)	1 cycles 2 cycles 3 cycles	3 cycles	Column Latency
tRFC (cycles)	tRFC must be between 2 and 4096 cycles	937	Auto-Refresh Request Interval Setting
tREFW (cycles)	Refer to the RA Configuration tool for available options.	8 cycles	Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
SDRAM > Initialization
Auto-Refresh Interval (ARFI)	Refer to the RA Configuration tool for available options.	10 cycles	Specifies the interval at which the auto-refresh commands are issued in the SDRAM initialization sequence.
Auto-Refresh Count (ARFC)	Refer to the RA Configuration tool for available options.	8 times	Specifies the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
Precharge Cycle Count (PRC)	3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles	3 cycles	Specifies the number of precharged cycles in the SDRAM initialization sequence.
SDRAM Support	Enabled Disabled	Disabled	If enabled, SDRAM will be initialized and configured by the BSP with the provided settings.
Address Multiplex Shift	8-bit shift 9-bit shift 10-bit shift 11-bit shift	9-bit shift	Selects the size of the shift towards the lower half of the row address in row address/column address multiplexing.
Endian Mode	Little Endian Big Endian	Little Endian	Specifies the endianness of the SDRAM address space. See HWM for full list of constraints when using Big Endian.
Continuous Access Mode	Enabled Disabled	Enabled	If enabled, SDRAM continuous access mode will be enabled.
Bus Width	8-bit 16-bit	16-bit	Specifies the data bus width for SDRAM.
OFS0 register settings
OFS0 register settings > Independent WDT
Start Mode	IWDT is stopped after a reset IWDT is automatically activated after a reset (Autostart mode)	IWDT is stopped after a reset
Timeout Period	128 cycles 512 cycles 1024 cycles 2048 cycles	2048 cycles
Dedicated Clock Frequency Divisor	1 16 32 64 128 256	128
Window End Position	75% 50% 25% 0% (no window end position)	0% (no window end position)
Window Start Position	25% 50% 75% 100% (no window start position)	100% (no window start position)
Reset Interrupt Request Select	NMI request or interrupt request is enabled Reset is enabled	Reset is enabled
Stop Control	Counting continues (Note: Device will not enter Deep Standby Mode when selected. Device will enter Software Standby Mode) Stop counting when in Sleep, Snooze mode, or Software Standby	Stop counting when in Sleep, Snooze mode, or Software Standby
OFS0 register settings > WDT
Start Mode Select	Automatically activate WDT after a reset (auto-start mode) Stop WDT after a reset (register-start mode)	Stop WDT after a reset (register-start mode)
Timeout Period	1024 cycles 4096 cycles 8192 cycles 16384 cycles	16384 cycles
Clock Frequency Division Ratio	4 64 128 512 2048 8192	128
Window End Position	75% 50% 25% 0% (no window end position)	0% (no window end position)
Window Start Position	25% 50% 75% 100% (no window start position)	100% (no window start position)
Reset Interrupt Request	NMI Reset	Reset
Stop Control	Counting continues Stop counting when entering Sleep mode	Stop counting when entering Sleep mode
OFS1 register settings
Voltage Detection 0 Circuit Start	Voltage monitor 0 reset is enabled after reset Voltage monitor 0 reset is disabled after reset	Voltage monitor 0 reset is disabled after reset
Voltage Detection 0 Level	2.94 V 2.87 V 2.80 V	2.80 V
HOCO Oscillation Enable	HOCO oscillation is enabled after reset HOCO oscillation is disabled after reset	HOCO oscillation is disabled after reset
MPU
Enable or disable PC Region 0	Enabled Disabled	Disabled
PC0 Start	Value must be an integer between 0 and 0xFFFFFFFC	0xFFFFFFFC
PC0 End	Value must be an integer between 0x00000003 and 0xFFFFFFFF	0xFFFFFFFF
Enable or disable PC Region 1	Enabled Disabled	Disabled
PC1 Start	Value must be an integer between 0 and 0xFFFFFFFC	0xFFFFFFFC
PC1 End	Value must be an integer between 0x00000003 and 0xFFFFFFFF	0xFFFFFFFF
Enable or disable Memory Region 0	Enabled Disabled	Disabled
Memory Region 0 Start	Value must be an integer between 0 and 0x00FFFFFC	0x00FFFFFC
Memory Region 0 End	Value must be an integer between 0x00000003 and 0x00FFFFFF	0x00FFFFFF
Enable or disable Memory Region 1	Enabled Disabled	Disabled
Memory Region 1 Start	Value must be an integer between 0x1FF00000 and 0x200FFFFC	0x200FFFFC
Memory Region 1 End	Value must be an integer between 0x1FF00003 and 0x200FFFFF	0x200FFFFF
Enable or disable Memory Region 2	Enabled Disabled	Disabled
Memory Region 2 Start	Value must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC	0x407FFFFC
Memory Region 2 End	Value must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF	0x407FFFFF
Enable or disable Memory Region 3	Enabled Disabled	Disabled
Memory Region 3 Start	Value must be an integer between 0x400C0000 and 0x400DFFFC or between 0x40100000 and 0x407FFFFC	0x400DFFFC
Memory Region 3 End	Value must be an integer between 0x400C0003 and 0x400DFFFF or between 0x40100003 and 0x407FFFFF	0x400DFFFF
Clocks
HOCO FLL Function	Enabled Disabled	Disabled	Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions. The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup. When FLL is enabled Software Standby and Deep Software Standby modes are not available.
Enable inline BSP IRQ functions	Enabled Disabled	Enabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Main Oscillator Wait Time	35 cycles 67 cycles 131 cycles 259 cycles 547 cycles 1059 cycles 2147 cycles 4291 cycles 8163 cycles	8163 cycles	Number of cycles to wait for the main oscillator clock to stabilize. Drive capability automatic switching function is by default disabled.
ID Code Mode	Unlocked (Ignore ID) Locked with All Erase support Locked	Unlocked (Ignore ID)	When set to 'Locked with All Erase support', the ID Code must be set in the debugger to read or write data to the MCU, but the All Erase command is still accepted regardless. When set to 'Locked', all erase/download/debug access is disabled unless the ID Code is provided.
ID Code (32 Hex Characters)	Value must be a 32 character long hex string	FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF	Set the ID Code for locking debug access. This setting is only used when the ID Code Mode is not set to Unlocked.

Macros
#define	BSP_ELC_PERIPHERAL_MASK

Enumerations
enum	elc_event_t
enum	elc_peripheral_t

Macro Definition Documentation

BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note

This list is device specific.

elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note

This list is device specific.