RA6M3

Detailed Description

Build Time Configurations for ra6m3_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
SDRAM
SDRAM > Timings
tRAS (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles	6 cycles	Row Active Interval
tRCD (cycles)	1 cycles 2 cycles 3 cycles 4 cycles	3 cycles	Row Column Latency
tRP (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles	3 cycles	Row Precharge Interval
tWR (cycles)	1 cycles 2 cycles	2 cycles	Write Recovery Interval
tCL (cycles)	1 cycles 2 cycles 3 cycles	3 cycles	Column Latency
tRFC (cycles)	tRFC must be between 2 and 4096 cycles	937	Auto-Refresh Request Interval Setting
tREFW (cycles)	Refer to the RA Configuration tool for available options.	8 cycles	Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
SDRAM > Initialization
Auto-Refresh Interval (ARFI)	Refer to the RA Configuration tool for available options.	10 cycles	Specifies the interval at which the auto-refresh commands are issued in the SDRAM initialization sequence.
Auto-Refresh Count (ARFC)	Refer to the RA Configuration tool for available options.	8 times	Specifies the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
Precharge Cycle Count (PRC)	3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles	3 cycles	Specifies the number of precharged cycles in the SDRAM initialization sequence.
SDRAM Support	Enabled Disabled	Disabled	If enabled, SDRAM will be initialized and configured by the BSP with the provided settings.
Address Multiplex Shift	8-bit shift 9-bit shift 10-bit shift 11-bit shift	9-bit shift	Selects the size of the shift towards the lower half of the row address in row address/column address multiplexing.
Endian Mode	Little Endian Big Endian	Little Endian	Specifies the endianness of the SDRAM address space. See HWM for full list of constraints when using Big Endian.
Continuous Access Mode	Enabled Disabled	Enabled	If enabled, SDRAM continuous access mode will be enabled.
Bus Width	8-bit 16-bit	16-bit	Specifies the data bus width for SDRAM.
Clocks
HOCO FLL Function	Enabled Disabled	Disabled	Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions. The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup. When FLL is enabled Software Standby and Deep Software Standby modes are not available.
MOSC Drive Capability Auto Switching	Enabled Disabled	Disabled	When enabled, the drive capability auto switching function lowers the MOSC drive capability automatically after the MOSC starts and suppresses the EMI associated with the MOSC.
Main Oscillator Wait Time	35 cycles 67 cycles 131 cycles 259 cycles 547 cycles 1059 cycles 2147 cycles 4291 cycles 8163 cycles	8163 cycles	Number of cycles to wait for the main oscillator clock to stabilize.
Enable inline BSP IRQ functions	Enabled Disabled	Enabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.

Macros
#define	BSP_ELC_PERIPHERAL_MASK

Enumerations
enum	elc_event_t
enum	elc_peripheral_t

Macro Definition Documentation

BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note

This list is device specific.

elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note

This list is device specific.