RA6T2

Detailed Description

Build Time Configurations for ra6t2_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
Security
Security > Exceptions
Exception Response	Non-Maskable Interrupt Reset	Non-Maskable Interrupt	Configure the result of a TrustZone Filter exception. This exception is generated when a the TrustZone Filter detects access to a protected region. This setting is only valid when building projects with TrustZone.
BusFault, HardFault, and NMI Target	Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit BFHFNMINS. Defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This setting is only valid when building projects with TrustZone.
Prioritize Secure Exceptions	Enabled Disabled	Disabled	Value for SCB->AIRCR register bit PRIS. When enabled, all Non-secure interrupt priorities are automatically demoted by right shifting their priority by one then setting the most significant bit. As there is effectively one less bit care must be taken to ensure the prioritization of non-secure interrupts is correct. This setting is only valid when building projects with TrustZone.
Security > SRAM Accessibility
SRAM Protection	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAMPRCR is write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
SRAM ECC	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAM ECC registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Standby RAM	Regions 7-0 are all Secure. Region 7 is Non-secure. Regions 6-0 are Secure. Regions 7-6 are Non-secure. Regions 5-0 are Secure. Regions 7-5 are Non-secure. Regions 4-0 are Secure. Regions 7-4 are Non-secure. Regions 3-0 are Secure. Regions 7-3 are Non-secure. Regions 2-0 are Secure. Regions 7-2 are Non-secure. Regions 1-0 are Secure. Regions 7-1 are Non-secure. Region 0 is Secure. Regions 7-0 are all Non-secure.	config.bsp.fsp.tz.stbramsar.both	Defines whether Standby RAM registers are accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Security > BUS Accessibility
Bus Security Attribution Register A	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Slave Bus Control Registers (BUSSCNT<slave>) are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register B	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Bus and DMAC/DTC Error Clear Registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
System Reset Request Accessibility	Both Secure and Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit SYSRESETREQS. Defines whether the SYSRESETREQ bit is functional for Non-secure use. This setting is only valid when building projects with TrustZone.
Cache Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Cache registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
System Reset Status Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the reset status registers (RSTSRn) can be cleared from the Non-secure application. This setting is only valid when building projects with TrustZone.
Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback Disable Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback	If enabled, the secure application checks if the non-secure application has been programmed in non-secure flash before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM. This prevents an issue where the debugger may not connect if the MCU is configured in the NSECSD lifecycle state.
Enable inline BSP IRQ functions	Enabled Disabled	Enabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Startup C-Cache Line Size	32 Bytes 64 Bytes	32 Bytes	Set the C-Cache line size configured during startup.
TFU Mathlib	Disabled Enabled	Enabled	If enabled, trigonometric library functions sinf, cosf, atan2f, and hypotf are replaced with hardware accelerated TFU functions. Disable this if reentrant access to these functions is required.
Main Oscillator Wait Time	3 cycles 35 cycles 67 cycles 131 cycles 259 cycles 547 cycles 1059 cycles 2147 cycles 4291 cycles 8163 cycles	8163 cycles	Number of cycles to wait for the main oscillator clock to stabilize.

Macros
#define	BSP_ELC_PERIPHERAL_MASK

Enumerations
enum	elc_event_t
enum	elc_peripheral_t

Macro Definition Documentation

BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note

This list is device specific.

elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note

This list is device specific.