RA8D1

Detailed Description

Build Time Configurations for ra8d1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
SDRAM
SDRAM > Timings
tRAS (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles	6 cycles	Row Active Interval
tRCD (cycles)	1 cycles 2 cycles 3 cycles 4 cycles	3 cycles	Row Column Latency
tRP (cycles)	1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles	3 cycles	Row Precharge Interval
tWR (cycles)	1 cycles 2 cycles	2 cycles	Write Recovery Interval
tCL (cycles)	1 cycles 2 cycles 3 cycles	3 cycles	Column Latency
tRFC (cycles)	tRFC must be between 2 and 4096 cycles	937	Auto-Refresh Request Interval Setting
tREFW (cycles)	Refer to the RA Configuration tool for available options.	8 cycles	Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
SDRAM > Initialization
Auto-Refresh Interval (ARFI)	Refer to the RA Configuration tool for available options.	10 cycles	Specifies the interval at which the auto-refresh commands are issued in the SDRAM initialization sequence.
Auto-Refresh Count (ARFC)	Refer to the RA Configuration tool for available options.	8 times	Specifies the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
Precharge Cycle Count (PRC)	3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 9 cycles 10 cycles	3 cycles	Specifies the number of precharged cycles in the SDRAM initialization sequence.
SDRAM Support	Enabled Disabled	Disabled	If enabled, SDRAM will be initialized and configured by the BSP with the provided settings.
Address Multiplex Shift	8-bit shift 9-bit shift 10-bit shift 11-bit shift	9-bit shift	Selects the size of the shift towards the lower half of the row address in row address/column address multiplexing.
Endian Mode	Little Endian Big Endian	Little Endian	Specifies the endianness of the SDRAM address space. See HWM for full list of constraints when using Big Endian.
Continuous Access Mode	Enabled Disabled	Enabled	If enabled, SDRAM continuous access mode will be enabled.
Bus Width	8-bit 16-bit 32-bit	16-bit	Specifies the data bus width for SDRAM.
Security
Security > Exceptions
Exception Response	Non-Maskable Interrupt Reset	Non-Maskable Interrupt	Configure the result of a TrustZone Filter exception. This exception is generated when a the TrustZone Filter detects access to a protected region. This setting is only valid when building projects with TrustZone.
BusFault, HardFault, and NMI Target	Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit BFHFNMINS. Defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This setting is only valid when building projects with TrustZone.
Prioritize Secure Exceptions	Enabled Disabled	Disabled	Value for SCB->AIRCR register bit PRIS. When enabled, all Non-secure interrupt priorities are automatically demoted by right shifting their priority by one then setting the most significant bit. As there is effectively one less bit care must be taken to ensure the prioritization of non-secure interrupts is correct. This setting is only valid when building projects with TrustZone.
Security > SRAM Accessibility
SRAM0 Protection	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAMCR0, SRAMECCRGN0, SRAMESCLR.CLR00, and SRAMESCLR.CLR01 are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
SRAM1 Protection	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAMCR1, and SRAMESCLR.CLR1 are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Standby SRAM Protection	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether STBRAMCR, and SRAMESCLR.CLRS are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Security > BUS Accessibility
Bus Security Attribution Register A	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Slave Bus Control Registers (BUSSCNT<slave>) are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register B	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Bus and DMAC/DTC Error Clear Registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register C	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the SDRAM/CSC Control registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
System Reset Request Accessibility	Both Secure and Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit SYSRESETREQS. Defines whether the SYSRESETREQ bit is functional for Non-secure use. This setting is only valid when building projects with TrustZone.
System Reset Status Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the reset status registers (RSTSRn) can be cleared from the Non-secure application. This setting is only valid when building projects with TrustZone.
Battery Backup Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the battery backup registers are accessible for the Non-secure application. If Secure State is selected, all battery backup registers are read only except for VBTBKRn registers which are both read and write protected. This setting is only valid when building projects with TrustZone.
Flash Bank Select Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the BANKSEL register is write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Graphics Power Domain Security Attribution	Both Secure and Non-Secure State Secure State	Secure State	Defines whether the PDCTRGD register is write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback Disable Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback	If enabled, the secure application checks if the non-secure application has been programmed in non-secure flash before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM. This prevents an issue where the debugger may not connect if the MCU is configured in the NSECSD lifecycle state.
OFS0 register settings
OFS0 register settings > Independent WDT
Start Mode	IWDT is stopped after a reset (Register-start mode) IWDT is automatically activated after a reset (Autostart mode)	IWDT is stopped after a reset (Register-start mode)
Timeout Period	128 cycles 512 cycles 1024 cycles 2048 cycles	2048 cycles
Dedicated Clock Frequency Divisor	1 16 32 64 128 256	128
Window End Position	75% 50% 25% 0% (no window end position)	0% (no window end position)
Window Start Position	25% 50% 75% 100% (no window start position)	100% (no window start position)
Reset Interrupt Request Select	NMI request or interrupt request is enabled Reset is enabled	Reset is enabled
Stop Control	Counting continues (Note: Device will not enter Deep Standby Mode when selected. Device will enter Software Standby Mode) Stop counting when in Sleep, Deep Sleep, or Software Standby	Stop counting when in Sleep, Deep Sleep, or Software Standby
OFS0 register settings > WDT0
Start Mode Select	Automatically activate WDT after a reset (auto-start mode) Stop WDT after a reset (register-start mode)	Stop WDT after a reset (register-start mode)
Timeout Period	1024 cycles 4096 cycles 8192 cycles 16384 cycles	16384 cycles
Clock Frequency Division Ratio	4 64 128 512 2048 8192	128
Window End Position	75% 50% 25% 0% (no window end position)	0% (no window end position)
Window Start Position	25% 50% 75% 100% (no window start position)	100% (no window start position)
Reset Interrupt Request	NMI Reset	Reset
Stop Control	Counting continues Stop counting when entering Sleep mode	Stop counting when entering Sleep mode
OFS1_SEL register settings
Voltage Detection 0 Level Security Attribution	VDSEL setting loads from OFS1_SEC VDSEL setting loads from OFS1	VDSEL setting loads from OFS1_SEC
Voltage Detection 0 Circuit Start Security Attribution	PVDAS setting loads from OFS1_SEC PVDAS setting loads from OFS1	PVDAS setting loads from OFS1_SEC
Voltage Detection 0 Low Power Consumption Security Attribution	PVDLPSEL setting loads from OFS1_SEC PVDLPSEL setting loads from OFS1	PVDLPSEL setting loads from OFS1_SEC
WDT/IWDT Software Debug Control Security Attribution	SWDBG setting loads from OFS1_SEC SWDBG setting loads from OFS1	SWDBG setting loads from OFS1_SEC
Tightly Coupled Memory (TCM)/Cache ECC Security Attribution	INITECCEN setting loads from OFS1_SEC INITECCEN setting loads from OFS1	INITECCEN setting loads from OFS1_SEC
OFS1 register settings
Voltage Detection 0 Circuit Start	Voltage monitor 0 reset is enabled after reset Voltage monitor 0 reset is disabled after reset	Voltage monitor 0 reset is disabled after reset
Voltage Detection 0 Level	2.85 V 2.58 V 2.15 V 2.00 V 1.90 V 1.80 V 1.70 V 1.60 V	1.60 V
Voltage Detection 0 Low Power Consumption	Voltage monitor 0 Low Power Consumption Enabled Voltage monitor 0 Low Power Consumption Disabled	Voltage monitor 0 Low Power Consumption Disabled	Enable or disable the low power consumption function of LVD0 during Deep Software Standby 1 and Deep Software Standby 2.
HOCO Oscillation Enable	HOCO oscillation is enabled after reset HOCO oscillation is disabled after reset	HOCO oscillation is disabled after reset
WDT/IWDT Software Debug Control	Enabled (WDT and IWDT operation is halted when the CPU is in the debug state) Disabled (WDT and IWDT continue operating while the CPU is in the debug state)	Disabled (WDT and IWDT continue operating while the CPU is in the debug state)
Tightly Coupled Memory (TCM)/Cache ECC	Enable ECC function for TCM and Cache Disable ECC function for TCM and Cache	Disable ECC function for TCM and Cache
OFS2 register settings
DCDC	Disabled Enabled	Enabled
Block Protection Settings (BPS)
BPS0	Refer to the RA Configuration tool for available options.	0U	Configure Block Protection Register 0
BPS1	Refer to the RA Configuration tool for available options.	0U	Configure Block Protection Register 1
BPS2	Refer to the RA Configuration tool for available options.	0U	Configure Block Protection Register 2
BPS3	Refer to the RA Configuration tool for available options.	0U	Configure Block Protection Register 3
Permanent Block Protection Settings (PBPS)
PBPS0	Refer to the RA Configuration tool for available options.	0U	Configure Permanent Block Protection Register 0
PBPS1	Refer to the RA Configuration tool for available options.	0U	Configure Permanent Block Protection Register 1
PBPS2	Refer to the RA Configuration tool for available options.	0U	Configure Permanent Block Protection Register 2
PBPS3	Refer to the RA Configuration tool for available options.	0U	Configure Permanent Block Protection Register 3
First Stage Bootloader (FSBL)
First Stage Bootloader (FSBL) > FSBL Control 0 (FSBLCTRL0)
FSBLEN	Enabled Disabled	Disabled	FSBL enable
FSBLSKIPSW	Enabled Disabled	Disabled	FSBL skip enable for software reset
FSBLSKIPDS	Enabled Disabled	Disabled	FSBL skip enable for deep software standby reset
FSBLCLK	120 MHz 240 MHz	240 MHz	Clock frequency selection during FSBL execution.
First Stage Bootloader (FSBL) > FSBL Control 1 (FSBLCTRL1)
FSBLEXMDFSBLEN	CRC boot without report CRC boot with report measurement Secure boot without report Secure boot with report measurement	Secure boot with report measurement	FSBL execution mode
First Stage Bootloader (FSBL) > FSBL Control 2 (FSBLCTRL2)
PORTPN	Refer to the RA Configuration tool for available options.	PORTn15	FSBL error notification port pin number
PORTGN	Refer to the RA Configuration tool for available options.	None	FSBL error notification port group name
First Stage Bootloader (FSBL) > Code Certificates (SACCn)
SACC0	Must be an integer between 0 and 0xFFFFFFFF.	0xFFFFFFFF	Start address of code certificate 0
SACC1	Must be an integer between 0 and 0xFFFFFFFF.	0xFFFFFFFF	Start address of code certificate 1
FSBL Measurement Report Address (SAMR)	Must be an integer between 0 and 0xFFFFFFFF.	0xFFFFFFFF	Start address of measurement report
Clocks
HOCO FLL Function	Enabled Disabled	Disabled	Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions. The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup. When FLL is enabled Software Standby and Deep Software Standby modes are not available.
Clock Settling Delay	Enabled Disabled	Enabled	Setting this option to Enabled will insert delays for clocking scaling and transitions to ensure voltage supply stability. See the RA8D1 HWM (R01UH0995EJ0100) section 8.11.1 for details.
Sleep Mode Entry and Exit Delays	Enabled Disabled	Enabled	Setting this option to Enabled will insert delays before and after entering sleep modes to ensure voltage supply stability. This is not required if you do not intend to run CPUCLK over 100MHz. See RA8D1 HWM (R01UH0995EJ0100) Section 10.8.10 for details.
RTOS Sleep on Idle	Enabled Disabled	Disabled	Setting this option to Enabled will allow RTOS ports to enter CPU Sleep mode while idle. This should not be used when CPUCLK is configured over 120MHz. See RA8M1 HWM (R01UH0994EJ0100) Section 10.7.10 for details.
MSTP Change Delays	Enabled Disabled	Enabled	Setting this option to Enabled will insert delays after setting a MSTP bit to ensure voltage supply stability. This is not required if you do not intend to run CPUCLK over 120MHz. See RA8D1 HWM (R01UH0995EJ0100) Section 10.4 for details.
Settling Delay (us)	Unit must be a non-negative integer	150	Specifies the length of the delay to be used for the Clock settling, Sleep mode, and MSTP change delays.
Cache settings
Data cache	Enabled Disabled	Disabled	Enable limited D-Cache support. See BSP usage notes for limitations.
Enable inline BSP IRQ functions	Enabled Disabled	Enabled	Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Dual Bank Mode	Enabled Disabled	Disabled	Enabling dual bank mode splits the flash into two banks that can be swapped by programming the BANKSEL non-volatile register. When enabled, one bank will start at address 0x0 and the other will start at 0x200000. Each bank contains exactly half the capacity of the entire code flash. When Dual Bank mode is enabled, Startup Program Protection and Block Swap functions cannot be used.
Main Oscillator Wait Time	3 cycles 35 cycles 67 cycles 131 cycles 259 cycles 547 cycles 1059 cycles 2147 cycles 4291 cycles 8163 cycles	8163 cycles	Number of cycles to wait for the main oscillator clock to stabilize.

Macros
#define	BSP_ELC_PERIPHERAL_MASK

Enumerations
enum	elc_event_t
enum	elc_peripheral_t

Macro Definition Documentation

BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note

This list is device specific.

elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note

This list is device specific.