RA Flexible Software Package Documentation  Release v6.0.0

 
Macros | Enumerations
RA8M1
BSP » MCU Board Support Package

Detailed Description

Build Time Configurations for ra8m1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

ConfigurationOptionsDefaultDescription
SDRAM
SDRAM > Timings
tRAS (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
6 cycles Row Active Interval
tRCD (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
3 cycles Row Column Latency
tRP (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
  • 8 cycles
3 cycles Row Precharge Interval
tWR (cycles)
  • 1 cycles
  • 2 cycles
2 cycles Write Recovery Interval
tCL (cycles)
  • 1 cycles
  • 2 cycles
  • 3 cycles
3 cycles Column Latency
tRFC (cycles)tRFC must be between 2 and 4096 cycles937 Auto-Refresh Request Interval Setting
tREFW (cycles)Refer to the RA Configuration tool for available options.8 cycles Auto-Refresh Cycle/Self-Refresh Clearing Cycle Count Setting.
SDRAM > Initialization
Auto-Refresh Interval (ARFI)Refer to the RA Configuration tool for available options.10 cycles Specifies the interval at which the auto-refresh commands are issued in the SDRAM initialization sequence.
Auto-Refresh Count (ARFC)Refer to the RA Configuration tool for available options.8 times Specifies the number of times auto-refresh is to be performed in the SDRAM initialization sequence.
Precharge Cycle Count (PRC)
  • 3 cycles
  • 4 cycles
  • 5 cycles
  • 6 cycles
  • 7 cycles
  • 8 cycles
  • 9 cycles
  • 10 cycles
3 cycles Specifies the number of precharged cycles in the SDRAM initialization sequence.
SDRAM Support
  • Enabled
  • Disabled
Disabled If enabled, SDRAM will be initialized and configured by the BSP with the provided settings.
Address Multiplex Shift
  • 8-bit shift
  • 9-bit shift
  • 10-bit shift
  • 11-bit shift
9-bit shift Selects the size of the shift towards the lower half of the row address in row address/column address multiplexing.
Endian Mode
  • Little Endian
  • Big Endian
Little Endian Specifies the endianness of the SDRAM address space. See HWM for full list of constraints when using Big Endian.
Continuous Access Mode
  • Enabled
  • Disabled
Enabled If enabled, SDRAM continuous access mode will be enabled.
Bus Width
  • 8-bit
  • 16-bit
  • 32-bit
16-bit Specifies the data bus width for SDRAM.
Security
Security > Exceptions
Exception Response
  • Non-Maskable Interrupt
  • Reset
Non-Maskable Interrupt Configure the result of a TrustZone Filter exception. This exception is generated when a the TrustZone Filter detects access to a protected region.

This setting is only valid when building projects with TrustZone.
BusFault, HardFault, and NMI Target
  • Non-Secure State
  • Secure State
Secure State Value for SCB->AIRCR register bit BFHFNMINS. Defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception.

This setting is only valid when building projects with TrustZone.
Prioritize Secure Exceptions
  • Enabled
  • Disabled
Disabled Value for SCB->AIRCR register bit PRIS. When enabled, all Non-secure interrupt priorities are automatically demoted by right shifting their priority by one then setting the most significant bit. As there is effectively one less bit care must be taken to ensure the prioritization of non-secure interrupts is correct.

This setting is only valid when building projects with TrustZone.
Security > SRAM Accessibility
SRAM0 Protection
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether SRAMCR0, SRAMECCRGN0, SRAMESCLR.CLR00, and SRAMESCLR.CLR01 are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
SRAM1 Protection
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether SRAMCR1, and SRAMESCLR.CLR1 are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Standby SRAM Protection
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether STBRAMCR, and SRAMESCLR.CLRS are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Security > BUS Accessibility
Bus Security Attribution Register A
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the Slave Bus Control Registers (BUSSCNT<slave>) are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register B
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the Bus and DMAC/DTC Error Clear Registers are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register C
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the SDRAM/CSC Control registers are write accessible for the Non-secure application.

This setting is only valid when building projects with TrustZone.
System Reset Request Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Secure State Value for SCB->AIRCR register bit SYSRESETREQS. Defines whether the SYSRESETREQ bit is functional for Non-secure use.

This setting is only valid when building projects with TrustZone.
System Reset Status Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the reset status registers (RSTSRn) can be cleared from the Non-secure application.

This setting is only valid when building projects with TrustZone.
Battery Backup Accessibility
  • Both Secure and Non-Secure State
  • Secure State
Both Secure and Non-Secure State Defines whether the battery backup registers are accessible for the Non-secure application. If Secure State is selected, all battery backup registers are read only except for VBTBKRn registers which are both read and write protected.

This setting is only valid when building projects with TrustZone.
Uninitialized Non-Secure Application Fallback
  • Enable Uninitialized Non-Secure Application Fallback
  • Disable Uninitialized Non-Secure Application Fallback
Enable Uninitialized Non-Secure Application Fallback If enabled, the secure application checks if the non-secure application has been programmed in non-secure flash before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM. This prevents an issue where the debugger may not connect if the MCU is configured in the NSECSD lifecycle state.
Clocks
HOCO FLL Function
  • Enabled
  • Disabled
Disabled Setting this option to Enabled improves HOCO accuracy significantly by using the subclock, but incurs certain restrictions.

The FLL function requires the subclock oscillator to be running and stabilized. When enabled and running the PLL or system clock from HOCO, the BSP will wait for both the Subclock Stabilization Time as well as the FLL Stabilization Time when setting up clocks at startup.

When FLL is enabled Software Standby and Deep Software Standby modes are not available.
Clock Settling Delay
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays for clocking scaling and transitions to ensure voltage supply stability. See the RA8M1 HWM (R01UH0994EJ0100) section 8.11.1 for details.
Sleep Mode Entry and Exit Delays
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays before and after entering sleep modes to ensure voltage supply stability. This is not required if you do not intend to run CPUCLK over 120MHz. See RA8M1 HWM (R01UH0994EJ0100) Section 10.7.10 for details.
RTOS Sleep on Idle
  • Enabled
  • Disabled
Disabled Setting this option to Enabled will allow RTOS ports to enter CPU Sleep mode while idle. This should not be used when CPUCLK is configured over 120MHz. See RA8M1 HWM (R01UH0994EJ0100) Section 10.7.10 for details.
MSTP Change Delays
  • Enabled
  • Disabled
Enabled Setting this option to Enabled will insert delays after setting a MSTP bit to ensure voltage supply stability. This is not required if you do not intend to run CPUCLK over 120MHz. See RA8M1 HWM (R01UH0994EJ0100) Section 10.4 for details.
Settling Delay (us)Unit must be a non-negative integer150 Specifies the length of the delay to be used for the Clock settling, Sleep mode, and MSTP change delays.
Cache settings
Data cache
  • Enabled
  • Disabled
Disabled Enable limited D-Cache support. See BSP usage notes for limitations.
Enable inline BSP IRQ functions
  • Enabled
  • Disabled
Enabled Using static inline functions will slightly increase code size, but will slightly decrease cycles taken in ISRs in return.
Main Oscillator Wait Time
  • 3 cycles
  • 35 cycles
  • 67 cycles
  • 131 cycles
  • 259 cycles
  • 547 cycles
  • 1059 cycles
  • 2147 cycles
  • 4291 cycles
  • 8163 cycles
8163 cycles Number of cycles to wait for the main oscillator clock to stabilize.
Enabled Hidden Property - Force D-Cache to use write-through for all cacheable writes.

Macros

#define BSP_ELC_PERIPHERAL_MASK
 

Enumerations

enum  elc_event_t
 
enum  elc_peripheral_t
 

Macro Definition Documentation

◆ BSP_ELC_PERIPHERAL_MASK

#define BSP_ELC_PERIPHERAL_MASK

Positions of event link set registers (ELSRs) available on this MCU

Enumeration Type Documentation

◆ elc_event_t

enum elc_event_t

Sources of event signals to be linked to other peripherals or the CPU

Note
This list is device specific.

◆ elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals

Note
This list is device specific.