RA Flexible Software Package Documentation  Release v6.1.0

 
Functions | Data Structures | Enumerations
Layer3 Ethernet Switch (r_layer3_switch)
Modules » Networking

Functions

fsp_err_t R_LAYER3_SWITCH_Open (ether_switch_ctrl_t *const p_ctrl, ether_switch_cfg_t const *const p_cfg)
 
fsp_err_t R_LAYER3_SWITCH_Close (ether_switch_ctrl_t *const p_ctrl)
 Disables interrupts and stop module. Implements ether_switch_api_t::close. More...
 
fsp_err_t R_LAYER3_SWITCH_CreateDescriptorQueue (ether_switch_ctrl_t *const p_ctrl, uint32_t *const p_queue_index, const layer3_switch_descriptor_queue_cfg_t *const p_queue_cfg)
 Create a new descriptor queue and set it to LINKFIX table. This function must be called before calling R_LAYER3_SWITCH_SetDescriptor and R_LAYER3_SWITCH_GetDescriptor. More...
 
fsp_err_t R_LAYER3_SWITCH_SetDescriptor (ether_switch_ctrl_t *const p_ctrl, uint32_t queue_index, const layer3_switch_descriptor_t *const p_descriptor)
 Set descripotor data to a target descriptor. More...
 
fsp_err_t R_LAYER3_SWITCH_GetDescriptor (ether_switch_ctrl_t *const p_ctrl, uint32_t queue_index, layer3_switch_descriptor_t *const p_descriptor)
 Get descripotor data from a target descriptor. More...
 
fsp_err_t R_LAYER3_SWITCH_StartDescriptorQueue (ether_switch_ctrl_t *const p_ctrl, uint32_t queue_index)
 Reload and enable a descriptor queue. In a TX descriptor queue, the queue start transmission. In a RX descriptor queue, the queue start reception. More...
 
fsp_err_t R_LAYER3_SWITCH_CallbackSet (ether_switch_ctrl_t *const p_ctrl, void(*p_callback)(ether_switch_callback_args_t *), void *const p_context, ether_switch_callback_args_t *const p_callback_memory)
 
fsp_err_t R_LAYER3_SWITCH_ConfigurePort (ether_switch_ctrl_t *const p_ctrl, uint8_t port, layer3_switch_port_cfg_t *p_port_cfg)
 
fsp_err_t R_LAYER3_SWITCH_AddTableEntry (ether_switch_ctrl_t *const p_ctrl, layer3_switch_frame_filter_t const *const p_target_frame, layer3_switch_table_entry_cfg_t const *const p_entry_cfg)
 
fsp_err_t R_LAYER3_SWITCH_SearchTableEntry (ether_switch_ctrl_t *const p_ctrl, layer3_switch_frame_filter_t const *const p_target_frame, layer3_switch_table_entry_cfg_t *const p_entry_cfg)
 
fsp_err_t R_LAYER3_SWITCH_ConfigureTable (ether_switch_ctrl_t *const p_ctrl, layer3_switch_table_cfg_t const *const p_table_cfg)
 
fsp_err_t R_LAYER3_SWITCH_GetTable (ether_switch_ctrl_t *const p_ctrl, layer3_switch_table_t *const p_table)
 
fsp_err_t R_LAYER3_SWITCH_ConfigureTAS (ether_switch_ctrl_t *const p_ctrl, uint8_t port, layer3_switch_tas_cfg_t *p_tas_cfg)
 
fsp_err_t R_LAYER3_SWITCH_EnableTAS (ether_switch_ctrl_t *const p_ctrl, uint8_t port)
 

Detailed Description

The LAYER3 SWITCH module (r_layer3_switch) provides an API for standard Ethernet communications applications that use the ESWM peripheral. It implements the Ethernet Switch Interface.

Overview

This module performs Ethernet frame transmission and reception using Ethernet Switch Module.

The following figure shows which IPs are used by the r_layer3_switch module.

r_layer3_switch_sw_and_hw_relation.png
ESWM block diagram

Features

The layer3 switch module supports the following features:

Configuration

Build Time Configurations for r_layer3_switch

The following build time configurations are defined in fsp_cfg/r_layer3_switch_cfg.h:

ConfigurationOptionsDefaultDescription
Parameter Checking
  • Default (BSP)
  • Enabled
  • Disabled
Default (BSP) If selected code for parameter checking is included in the build.
Available queue numValue must be an integer between 1 and 644 available queue num.
Time Aware Shaper
  • Enabled
  • Disabled
Disabled Select whether or not to use the Time Aware Shaper function.

Configurations for Networking > Switch (r_layer3_switch)

This module can be added to the Stacks tab via New Stack > Networking > Switch (r_layer3_switch). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

ConfigurationOptionsDefaultDescription
Interrupts
Interrupt priorityMCU Specific OptionsSelect the layer3_switch interrupt priority.
ETHA0 error interrupt priorityMCU Specific OptionsSelect the layer3_switch etha0 interrupt priority.
ETHA1 error interrupt priorityMCU Specific OptionsSelect the layer3_switch etha1 interrupt priority.
Ports
Ports > Port 0
Ports > Port 0 > IPV queue depth
Queue 0Value must be an integer more than 164 queue0 dept of port 0.
Queue 1Value must be an integer more than 164 queue1 dept of port 0.
Queue 2Value must be an integer more than 164 queue2 dept of port 0.
Queue 3Value must be an integer more than 164 queue3 dept of port 0.
Queue 4Value must be an integer more than 164 queue4 dept of port 0.
Queue 5Value must be an integer more than 164 queue5 dept of port 0.
Queue 6Value must be an integer more than 164 queue6 dept of port 0.
Queue 7Value must be an integer more than 164 queue7 dept of port 0.
FowardingMCU Specific OptionsDestination ports for port 0 fowarding
MAC addressMust be a valid MAC address00:11:22:33:44:55 MAC address of port 0.
CallbackName must be a valid C symbolNULL Callback provided when an ISR occurs for port0.
ContextName must be a valid C symbolNULL Placeholder for user data. Passed to the user callback in ether_switch_callback_args_t for port0.
Ports > Port 1
Ports > Port 1 > IPV queue depth
Queue 0Value must be an integer more than 164 queue0 dept of port 1.
Queue 1Value must be an integer more than 164 queue1 dept of port 1.
Queue 2Value must be an integer more than 164 queue2 dept of port 1.
Queue 3Value must be an integer more than 164 queue3 dept of port 1.
Queue 4Value must be an integer more than 164 queue4 dept of port 1.
Queue 5Value must be an integer more than 164 queue5 dept of port 1.
Queue 6Value must be an integer more than 164 queue6 dept of port 1.
Queue 7Value must be an integer more than 164 queue7 dept of port 1.
FowardingMCU Specific OptionsDestination ports for port 1 fowarding
MAC addressMust be a valid MAC address00:11:22:33:44:55 MAC address of port 1.
CallbackName must be a valid C symbolNULL Callback provided when an ISR occurs for port1.
ContextName must be a valid C symbolNULL Placeholder for user data. Passed to the user callback in ether_switch_callback_args_t for port1.
CBS
CBS > Port 0 Band width ( % )
Queue 0Value must be an integer between 0 and 1000 queue0 Band width of port 0.
Queue 1Value must be an integer between 0 and 1000 queue1 Band width of port 0.
Queue 2Value must be an integer between 0 and 1000 queue2 Band width of port 0.
Queue 3Value must be an integer between 0 and 1000 queue3 Band width of port 0.
Queue 4Value must be an integer between 0 and 1000 queue4 Band width of port 0.
Queue 5Value must be an integer between 0 and 1000 queue5 Band width of port 0.
Queue 6Value must be an integer between 0 and 1000 queue6 Band width of port 0.
Queue 7Value must be an integer between 0 and 1000 queue7 Band width of port 0.
CBS > Port 1 Band width ( % )
Queue 0Value must be an integer between 0 and 1000 queue0 Band width of port 1.
Queue 1Value must be an integer between 0 and 1000 queue1 Band width of port 1.
Queue 2Value must be an integer between 0 and 1000 queue2 Band width of port 1.
Queue 3Value must be an integer between 0 and 1000 queue3 Band width of port 1.
Queue 4Value must be an integer between 0 and 1000 queue4 Band width of port 1.
Queue 5Value must be an integer between 0 and 1000 queue5 Band width of port 1.
Queue 6Value must be an integer between 0 and 1000 queue6 Band width of port 1.
Queue 7Value must be an integer between 0 and 1000 queue7 Band width of port 1.
CBS > Port 0 Maximum burst frame number
Queue 0Value must be an integer between 0 and 2550 queue0 maximum burst frame number of port 0.
Queue 1Value must be an integer between 0 and 2550 queue1 maximum burst frame number of port 0.
Queue 2Value must be an integer between 0 and 2550 queue2 maximum burst frame number of port 0.
Queue 3Value must be an integer between 0 and 2550 queue3 maximum burst frame number of port 0.
Queue 4Value must be an integer between 0 and 2550 queue4 maximum burst frame number of port 0.
Queue 5Value must be an integer between 0 and 2550 queue5 maximum burst frame number of port 0.
Queue 6Value must be an integer between 0 and 2550 queue6 maximum burst frame number of port 0.
Queue 7Value must be an integer between 0 and 2550 queue7 maximum burst frame number of port 0.
CBS > Port 1 Maximum burst frame number
Queue 0Value must be an integer between 0 and 2550 queue0 maximum burst frame number of port 0.
Queue 1Value must be an integer between 0 and 2550 queue1 maximum burst frame number of port 0.
Queue 2Value must be an integer between 0 and 2550 queue2 maximum burst frame number of port 0.
Queue 3Value must be an integer between 0 and 2550 queue3 maximum burst frame number of port 0.
Queue 4Value must be an integer between 0 and 2550 queue4 maximum burst frame number of port 0.
Queue 5Value must be an integer between 0 and 2550 queue5 maximum burst frame number of port 0.
Queue 6Value must be an integer between 0 and 2550 queue6 maximum burst frame number of port 0.
Queue 7Value must be an integer between 0 and 2550 queue7 maximum burst frame number of port 0.
NameName must be a valid C symbolg_layer3_switch0 Module name.
Channel00 Select the layer3 switch controller channel number.
ContextName must be a valid C symbolNULL Placeholder for user data. Passed to the user callback in ether_switch_callback_args_t.
CallbackName must be a valid C symbolNULL Callback provided when an ISR occurs
Number of Layer 3 routing entriesValue must be an integer between 1 and 25610 Maximum number of Layer 3 routing entries.

Usage Notes

Time-Sensitive Network (TSN)

Credit Based Shaper [802.1Qav]

Credit Based Shaper (CBS) is a standard defined in IEEE 802.1Qav that limits the throughput of Ethernet traffic. The figure below illustrates the operation of CBS when the bandwidth is set to 40Mbps. When the transmission throughput exceeds the bandwidth configured by CBS, frame transmission is restricted. The restricted frames are buffered in the queue and transmitted with delay.

r_layer3_switch_cbs.png
CBS operation image

In the r_layer3_switch module, CBS bandwidth can be configured for each Internal Priority Value (IPV) queue per transmission port. There are 8 IPV queues available for each port. On transmission ports where CBS is enabled, the throughput is limited to the configured bandwidth. CBS can be configured through stack properties or the ConfigurePort() API.

Note
The maximum number of frames that can be buffered by CBS is limited to the depth of each IPV queue. If many frames are buffered in high-priority queues, the common memory pool may be depleted, potentially limiting transmission from other queues.

Time-Aware Shaper [802.1Qbv]

Time-Aware Shaper (TAS) is a standard defined in IEEE 802.1Qbv that limits Ethernet traffic by controlling the time window when frames are transmitted. TAS controls transmission by changing gate states. Frames are transmitted while the gate is opened and when the gate is closed, frames cannot be transmitted and are delayed until the next open state. By opening each gate at different timings, it is possible to prevent frames of specific priorities from monopolizing the bandwidth. The figure below illustrates the operation of TAS. In this image, the gate cycle time is set to 10ms, Gate 0 is opened for 2.5 ms and closed for 7.5 ms, Gate 1 is closed for 1.0 + 5.0 ms and open for 4.0 ms.

r_layer3_switch_tas.png
TAS operation image

In the r_layer3_switch module, TAS gates can be configured for each IPV queue of the transmission ports. Each gate learns entries that represent windows. An entry contains the window time and state. TAS feature is configured using the ConfigureTAS() API, and enabled using the EnableTAS() API.

Note
This TAS feature uses the gPTP timer.

Limitations

Developers should be aware of the following limitations when using the r_layer3_switch:

Examples

Basic Example

This is a basic example of transmission use of the LAYER3 SWITCH.

#define LAYER3_SWITCH_EXAMPLE_DESCRIPTOR_POOL_SIZE (8)
#define LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE (1514)
#define LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_UPPER ((uint8_t) ((LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE & \
0xFF00) >> 8))
#define LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_LOWER ((uint8_t) LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE & \
0x00FF)
#define LAYER3_SWITCH_EXAMPLE_TRANSMIT_ETHERNET_FRAME_SIZE (60)
#define LAYER3_SWITCH_EXAMPLE_SOURCE_MAC_ADDRESS 0x74, 0x90, 0x50, 0x00, 0x79, 0x01
#define LAYER3_SWITCH_EXAMPLE_DESTINATION_MAC_ADDRESS 0x74, 0x90, 0x50, 0x00, 0x79, 0x02
#define LAYER3_SWITCH_EXAMPLE_FRAME_TYPE 0x00, 0x2E
#define LAYER3_SWITCH_EXAMPLE_PAYLOAD 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, \
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
layer3_switch_descriptor_t gp_descriptor_pool[LAYER3_SWITCH_EXAMPLE_DESCRIPTOR_POOL_SIZE];
uint8_t gp_ether_buffer0[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer1[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer2[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer3[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer4[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer5[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer6[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t gp_ether_buffer7[LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE];
uint8_t * gpp_ether_buffers[8] =
{
&gp_ether_buffer0[0],
&gp_ether_buffer1[0],
&gp_ether_buffer2[0],
&gp_ether_buffer3[0],
&gp_ether_buffer4[0],
&gp_ether_buffer5[0],
&gp_ether_buffer6[0],
&gp_ether_buffer7[0],
};
/* Transmit data buffer */
uint8_t gp_send_data[LAYER3_SWITCH_EXAMPLE_TRANSMIT_ETHERNET_FRAME_SIZE] =
{
LAYER3_SWITCH_EXAMPLE_DESTINATION_MAC_ADDRESS, /* Destination MAC address */
LAYER3_SWITCH_EXAMPLE_SOURCE_MAC_ADDRESS, /* Source MAC address */
LAYER3_SWITCH_EXAMPLE_FRAME_TYPE, /* Type field */
LAYER3_SWITCH_EXAMPLE_PAYLOAD /* Payload value (46byte) */
};
void layer3_switch_transmit_example (void)
{
fsp_err_t err = FSP_SUCCESS;
uint32_t queue_index = 0;
/* Configure transmission queue. */
layer3_switch_descriptor_queue_cfg_t transmission_queue_cfg =
{
.descriptor_format = LAYER3_SWITCH_DISCRIPTOR_FORMTAT_EXTENDED,
.type = LAYER3_SWITCH_QUEUE_TYPE_TX,
.write_back_mode = LAYER3_SWITCH_WRITE_BACK_MODE_FULL,
.p_descriptor_array = gp_descriptor_pool,
.array_length = LAYER3_SWITCH_EXAMPLE_DESCRIPTOR_POOL_SIZE,
.ports = LAYER3_SWITCH_PORT_BITMASK_PORT0,
};
/* Prepare data for transmission. */
memcpy(gpp_ether_buffers[0], gp_send_data, LAYER3_SWITCH_EXAMPLE_TRANSMIT_ETHERNET_FRAME_SIZE);
/* Initialize transmission descriptor. */
layer3_switch_descriptor_t transmission_descriptor = {0};
transmission_descriptor.basic.ds_l = LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_LOWER;
transmission_descriptor.basic.ds_h = LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_UPPER;
transmission_descriptor.basic.die = 1;
transmission_descriptor.basic.ptr_l = (uintptr_t) gpp_ether_buffers;
transmission_descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE;
transmission_descriptor.info1_tx.fmt = 1;
transmission_descriptor.info1_tx.dv = LAYER3_SWITCH_PORT_BITMASK_PORT0;
/* Open the layer3 switch instance with initial configuration. */
err = R_LAYER3_SWITCH_Open(&g_layer3_switch0_ctrl, &g_layer3_switch0_cfg);
/* Handle any errors. This function should be defined by the user. */
assert(FSP_SUCCESS == err);
/* Initialize PHY-LSI chip. */
err = R_RMAC_PHY_ChipInit(&g_rmac_phy0_ctrl, &g_rmac_phy0_cfg);
assert(FSP_SUCCESS == err);
/* Start auto negotiation. */
err = R_RMAC_PHY_StartAutoNegotiate(&g_rmac_phy0_ctrl);
assert(FSP_SUCCESS == err);
do
{
/* Get the Ethernet link status read from the PHY-LSI Basic Status registers until link-up. */
err = R_RMAC_PHY_LinkStatusGet(&g_rmac_phy0_ctrl);
R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
} while (FSP_SUCCESS != err);
/* Create descriptor queue. */
err = R_LAYER3_SWITCH_CreateDescriptorQueue(&g_layer3_switch0_ctrl, &queue_index, &transmission_queue_cfg);
assert(FSP_SUCCESS == err);
/* Set descriptor to queue. */
err = R_LAYER3_SWITCH_SetDescriptor(&g_layer3_switch0_ctrl, queue_index, &transmission_descriptor);
assert(FSP_SUCCESS == err);
/* Start transmission. */
err = R_LAYER3_SWITCH_StartDescriptorQueue(&g_layer3_switch0_ctrl, queue_index);
assert(FSP_SUCCESS == err);
R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS);
/* Get descriptor status. */
err = R_LAYER3_SWITCH_GetDescriptor(&g_layer3_switch0_ctrl, queue_index, &transmission_descriptor);
assert(FSP_SUCCESS == err);
/* Check if transmission is completed. */
assert(LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY == transmission_descriptor.basic.dt);
/* Disable transmission and receive function and close the layer3 switch instance. */
R_LAYER3_SWITCH_Close(&g_layer3_switch0_ctrl);
assert(FSP_SUCCESS == err);
}

This is a basic example of reception use of the LAYER3 SWITCH.

#define LAYER3_SWITCH_EXAMPLE_RECEPTION_QUEUE_LENGTH (4)
bool g_complete_reception_flag;
void layer3_switch_receive_example (void)
{
fsp_err_t err = FSP_SUCCESS;
uint32_t queue_index = 1;
/* Configure reception queue. */
layer3_switch_descriptor_queue_cfg_t reception_queue_cfg =
{
.descriptor_format = LAYER3_SWITCH_DISCRIPTOR_FORMTAT_EXTENDED,
.type = LAYER3_SWITCH_QUEUE_TYPE_RX,
.write_back_mode = LAYER3_SWITCH_WRITE_BACK_MODE_FULL,
.p_descriptor_array = gp_descriptor_pool,
.array_length = LAYER3_SWITCH_EXAMPLE_DESCRIPTOR_POOL_SIZE,
.ports = LAYER3_SWITCH_PORT_BITMASK_PORT0,
};
/* Initialize reception descriptor. */
layer3_switch_descriptor_t reception_descriptor = {0};
reception_descriptor.basic.ds_l = LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_LOWER;
reception_descriptor.basic.ds_h = LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE_UPPER;
reception_descriptor.basic.die = 1;
reception_descriptor.basic.ptr_l = (uintptr_t) gpp_ether_buffers;
reception_descriptor.basic.dt = LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY;
reception_descriptor.info1_tx.fmt = 1;
reception_descriptor.info1_tx.dv = LAYER3_SWITCH_PORT_BITMASK_PORT0;
/* Open the layer3 switch instance with initial configuration. */
err = R_LAYER3_SWITCH_Open(&g_layer3_switch0_ctrl, &g_layer3_switch0_cfg);
assert(FSP_SUCCESS == err);
/* Initialize PHY-LSI chip. */
err = R_RMAC_PHY_ChipInit(&g_rmac_phy0_ctrl, &g_rmac_phy0_cfg);
assert(FSP_SUCCESS == err);
/* Start auto negotiation. */
err = R_RMAC_PHY_StartAutoNegotiate(&g_rmac_phy0_ctrl);
assert(FSP_SUCCESS == err);
do
{
/* Get the Ethernet link status read from the PHY-LSI Basic Status registers until link-up. */
err = R_RMAC_PHY_LinkStatusGet(&g_rmac_phy0_ctrl);
R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
} while (FSP_SUCCESS != err);
/* Create descriptor queue. */
err = R_LAYER3_SWITCH_CreateDescriptorQueue(&g_layer3_switch0_ctrl, &queue_index, &reception_queue_cfg);
assert(FSP_SUCCESS == err);
/* Copy descriptor to queue. */
for (uint16_t i = 0; i < LAYER3_SWITCH_EXAMPLE_RECEPTION_QUEUE_LENGTH - 1; i++)
{
memset(gpp_ether_buffers[i], 0, LAYER3_SWITCH_EXAMPLE_MAXIMUM_FRAME_SIZE);
reception_descriptor.basic.ptr_l = (uintptr_t) gpp_ether_buffers[i];
err = R_LAYER3_SWITCH_SetDescriptor(&g_layer3_switch0_ctrl, queue_index, &reception_descriptor);
assert(FSP_SUCCESS == err);
}
g_complete_reception_flag = false;
/* Start reception. */
err = R_LAYER3_SWITCH_StartDescriptorQueue(&g_layer3_switch0_ctrl, queue_index);
assert(FSP_SUCCESS == err);
/* Wait to complete reception. */
while (true != g_complete_reception_flag)
{
R_BSP_SoftwareDelay(10, BSP_DELAY_UNITS_MILLISECONDS);
}
/* Disable transmission and receive function and close the layer3 switch instance. */
R_LAYER3_SWITCH_Close(&g_layer3_switch0_ctrl);
assert(FSP_SUCCESS == err);
}
void layer3_switch_example_callback (ether_switch_callback_args_t * p_args) {
switch (p_args->event)
{
case ETHER_SWITCH_EVENT_RX_COMPLETE:
{
g_complete_reception_flag = true;
break;
}
case ETHER_SWITCH_EVENT_TX_COMPLETE:
{
break;
}
case ETHER_SWITCH_EVENT_RX_QUEUE_FULL:
{
break;
}
case ETHER_SWITCH_EVENT_RX_MESSAGE_LOST:
{
break;
}
default:
{
break;
}
}
}

TSN Example

The below is an example of forwarding frames with Credit Based Shaper (CBS).

void layer3_switch_cbs_example (void)
{
fsp_err_t err = FSP_SUCCESS;
uint8_t source_port = 0;
uint8_t destination_port = 1;
layer3_switch_port_cfg_t port_cfg = {0};
/* Set bandwidth of queue 0 to 30 Mbps, queue 1 to 20 Mbps. */
layer3_switch_cbs_cfg_t cbs_cfg =
{
.band_width_list = {30, 20, 0, 0, 0, 0, 0, 0 },
.max_burst_num_list = {10, 10, 10, 10, 10, 10, 10, 10 },
};
/* Destination of forwarding target frames are 00:01:02:03:04:05 and 10:11:12:13:14:15*/
uint8_t p_mac_address_list[2][6] =
{
{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, },
{0x10, 0x11, 0x12, 0x13, 0x14, 0x15, },
};
layer3_switch_table_cfg_t mac_table_cfg =
{
.port_cfg_list = {{.mac_table_enable = true}, {.mac_table_enable = true}},
.unsecure_entry_maximum_num = 2,
};
layer3_switch_frame_filter_t mac_entry_frame;
layer3_switch_table_entry_cfg_t mac_entry_cfg =
{
.destination_ports = (1 << destination_port),
.source_ports = (1 << source_port),
.internal_priority_update_enable = true,
.entry_enable = true,
};
/* Open the layer3 switch instance with initial configuration. */
err = R_LAYER3_SWITCH_Open(&g_layer3_switch0_ctrl, &g_layer3_switch0_cfg);
assert(FSP_SUCCESS == err);
/* Initialize MAC table entry.*/
mac_entry_frame.entry_type = LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC;
/* Reset MAC table. */
err = R_LAYER3_SWITCH_ConfigureTable(&g_layer3_switch0_ctrl, &mac_table_cfg);
assert(FSP_SUCCESS == err);
/* Learn destination MAC address of a forwarding frame. */
for (uint8_t i = 0; i < 2; i++)
{
mac_entry_frame.p_destination_mac_address = p_mac_address_list[i];
mac_entry_cfg.internal_priority_update_value = i;
err = R_LAYER3_SWITCH_AddTableEntry(&g_layer3_switch0_ctrl, &mac_entry_frame, &mac_entry_cfg);
assert(FSP_SUCCESS == err);
}
/* Configure and enable CBS. */
port_cfg.p_cbs_cfg = &cbs_cfg;
err = R_LAYER3_SWITCH_ConfigurePort(&g_layer3_switch0_ctrl, destination_port, &port_cfg);
assert(FSP_SUCCESS == err);
while (1)
{
R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS);
}
}

The below is an example of forwarding frames with Credit Based Shaper (TAS).

#define LAYER3_SWITCH_EXAMPLE_GPTP_TIMER (0)
#define LAYER3_SWITCH_EXAMPLE_GPTP_CLOCK_PERIOD (4)
void layer3_switch_tas_example (void)
{
fsp_err_t err = FSP_SUCCESS;
uint8_t source_port = 0;
uint8_t destination_port = 1;
layer3_switch_table_entry_t mac_table_entry;
layer3_switch_tas_cfg_t tas_cfg;
layer3_switch_tas_entry_t closed_entry_list[1] = {{.state = LAYER3_SWITCH_TAS_GATE_STATE_CLOSE, .time = 0}};
layer3_switch_tas_gate_cfg_t tas_gate_closed =
{
.tas_entry_num = 1, .initial_gate_state = LAYER3_SWITCH_TAS_GATE_STATE_CLOSE,
.p_tas_entry_list = closed_entry_list
};
gptp_instance_t const * p_gptp_instance = g_layer3_switch0_extended_cfg.p_gptp_instance;
gptp_timer_cfg_t timer_cfg = {.clock_period = LAYER3_SWITCH_EXAMPLE_GPTP_CLOCK_PERIOD};
/* Open the layer3 switch instance with initial configuration. */
err = R_LAYER3_SWITCH_Open(&g_layer3_switch0_ctrl, &g_layer3_switch0_cfg);
assert(FSP_SUCCESS == err);
/* Gate 0 and 1 are repeat Open/Close. Other gates are alwayes closed. */
tas_cfg.gate_cfg_list[0] = g_layer3_switch_example_tas_gate_0_cfg;
tas_cfg.gate_cfg_list[1] = g_layer3_switch_example_tas_gate_1_cfg;
for (uint8_t i = 2; i < 8; i++)
{
tas_cfg.gate_cfg_list[i] = tas_gate_closed;
}
tas_cfg.gptp_timer_number = LAYER3_SWITCH_EXAMPLE_GPTP_TIMER;
tas_cfg.cycle_time_start_high = LAYER3_SWITCH_EXAMPLE_CYCLE_START_TIME_UPPER_32BIT;
tas_cfg.cycle_time_start_low = LAYER3_SWITCH_EXAMPLE_CYCLE_START_TIME_UPPER_32BIT;
tas_cfg.cycle_time = LAYER3_SWITCH_EXAMPLE_CYCLE_TIME;
/* Start gPTP timer before enable TAS feature. */
p_gptp_instance->p_api->timerCfg(p_gptp_instance->p_ctrl, LAYER3_SWITCH_EXAMPLE_GPTP_TIMER, &timer_cfg);
p_gptp_instance->p_api->start(p_gptp_instance->p_ctrl, LAYER3_SWITCH_EXAMPLE_GPTP_TIMER);
/* Configure and enable TAS. */
err = R_LAYER3_SWITCH_ConfigureTAS(&g_layer3_switch0_ctrl, destination_port, &tas_cfg);
assert(FSP_SUCCESS == err);
err = R_LAYER3_SWITCH_EnableTAS(&g_layer3_switch0_ctrl, destination_port);
assert(FSP_SUCCESS == err);
/* Initialize MAC table entry.*/
err = R_LAYER3_SWITCH_ConfigureTable(&g_layer3_switch0_ctrl, &g_layer3_switch_example_mac_table_cfg);
assert(FSP_SUCCESS == err);
/* Learn a MAC entry. */
mac_table_entry.target_frame.entry_type = LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC;
mac_table_entry.entry_cfg.entry_enable = true;
mac_table_entry.entry_cfg.security_enable = true;
mac_table_entry.entry_cfg.destination_ports = (uint32_t) (1 << destination_port);
mac_table_entry.entry_cfg.source_ports = (1 << source_port);
mac_table_entry.entry_cfg.internal_priority_update_enable = true;
for (uint8_t i = 0; i < 2; i++)
{
mac_table_entry.target_frame.p_destination_mac_address = g_layer3_switch_example_mac_address_list[i];
mac_table_entry.entry_cfg.internal_priority_update_value = i;
err = R_LAYER3_SWITCH_AddTableEntry(&g_layer3_switch0_ctrl,
&mac_table_entry.target_frame,
&mac_table_entry.entry_cfg);
assert(FSP_SUCCESS == err);
}
while (1)
{
R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_MILLISECONDS);
}
}

Data Structures

struct  layer3_switch_basic_descriptor_t
 
struct  layer3_switch_descriptor_t
 
struct  layer3_switch_descriptor_queue_cfg_t
 
struct  layer3_switch_cbs_cfg_t
 
struct  layer3_switch_port_cfg_t
 
struct  layer3_switch_descriptor_queue_status_t
 
struct  layer3_switch_ipv6_filter_address_offset_t
 
struct  layer3_switch_l3_stream_filter_cfg_t
 
struct  layer3_switch_frame_vlan_tag_t
 
struct  layer3_switch_frame_filter_t
 
struct  layer3_switch_l3_filter_t
 
struct  layer3_switch_l3_update_config_t
 
struct  layer3_switch_table_entry_cfg_t
 
struct  layer3_switch_table_entry_t
 
struct  layer3_switch_forwarding_port_cfg_t
 
struct  layer3_switch_table_t
 
struct  layer3_switch_table_cfg_t
 
struct  layer3_switch_extended_cfg_t
 
struct  layer3_switch_instance_ctrl_t
 
struct  layer3_switch_tas_entry_t
 
struct  layer3_switch_tas_gate_cfg_t
 
struct  layer3_switch_tas_cfg_t
 

Enumerations

enum  layer3_switch_descriptor_type_t
 
enum  layer3_switch_port_bitmask_t
 
enum  layer3_switch_queue_type_t
 
enum  layer3_switch_descriptor_format_t
 
enum  layer3_switch_write_back_mode_t
 
enum  layer3_switch_ip_version_t
 
enum  layer3_switch_ip_address_direction_t
 
enum  layer3_switch_magic_packet_detection_t
 
enum  layer3_switch_vlan_mode_t
 
enum  layer3_switch_vlan_ingress_mode_t
 
enum  layer3_switch_vlan_egress_mode_t
 
enum  layer3_switch_ip_protocol_t
 
enum  layer3_switch_forwarding_r_tag_t
 
enum  layer3_switch_l3_filter_bitmask_t
 
enum  layer3_switch_l3_update_bitmask_t
 
enum  layer3_switch_table_entry_type_t
 
enum  layer3_switch_table_status_t
 
enum  layer3_switch_tas_gate_state_t
 

Data Structure Documentation

◆ layer3_switch_basic_descriptor_t

struct layer3_switch_basic_descriptor_t

GWCA descriptor.

◆ layer3_switch_descriptor_t

struct layer3_switch_descriptor_t

GWCA extended descriptor.

◆ layer3_switch_descriptor_queue_cfg_t

struct layer3_switch_descriptor_queue_cfg_t

Configuration of a descriptor queue.

Data Fields
layer3_switch_descriptor_format_t descriptor_format Enable or disable extended descriptors.
layer3_switch_queue_type_t type Reception queue or transmission queue.
layer3_switch_write_back_mode_t write_back_mode Configure write-back to descriptor fields.
layer3_switch_descriptor_t * p_descriptor_array Descriptor array that use to create queue.
uint32_t array_length Length of descriptor array. This length includes terminate descriptor at the end.
uint32_t ports Bitmap of ports that use this queue.

◆ layer3_switch_cbs_cfg_t

struct layer3_switch_cbs_cfg_t

Configuration of Credit Based Shaper.

Data Fields
uint8_t band_width_list[8] CBS band width [%] of each queue.
uint8_t max_burst_num_list[8] Maximum burst frame number of each queue.

◆ layer3_switch_port_cfg_t

struct layer3_switch_port_cfg_t

Configuration of each Ethernet port.

Data Fields

uint8_t * p_mac_address
 Pointer to MAC address.
 
bool forwarding_to_cpu_enable
 Enable or disable reception on CPU.
 
layer3_switch_cbs_cfg_t * p_cbs_cfg
 Pointer to CBS configuration.
 
void(* p_callback )(ether_switch_callback_args_t *p_args)
 Callback provided when an ISR occurs.
 
ether_switch_callback_args_t * p_callback_memory
 Pointer to optional callback argument memory.
 
void * p_context
 Pointer to context to be passed into callback function.
 

◆ layer3_switch_descriptor_queue_status_t

struct layer3_switch_descriptor_queue_status_t

Status of a descriptor queue.

Data Fields
uint32_t head Index at the head of the queue. This used for GetDescriptor API.
uint32_t tail Index at the tail of the queue. This used for SetDescriptor API.
bool created This queue is already created.
layer3_switch_descriptor_queue_cfg_t
const *		 p_queue_cfg Configuration of this queue.

◆ layer3_switch_ipv6_filter_address_offset_t

struct layer3_switch_ipv6_filter_address_offset_t

IP address offset for creating IPv6 filter of Layer3 forwarding.

Data Fields
uint8_t offset Offset of IPv6 address.
layer3_switch_ip_address_direction_t direction Select source or destination.

◆ layer3_switch_l3_stream_filter_cfg_t

struct layer3_switch_l3_stream_filter_cfg_t

Configuration of stream filter in Layer3 forwarding.

Data Fields
uint16_t filter_field_bitmask Bitmask of which feilds is enabled in stream filter. Use layer3_switch_l3_filter_bitmask_t.
layer3_switch_ipv6_filter_address_offset_t ipv6_address0 Offset of IPv6 address 0.
layer3_switch_ipv6_filter_address_offset_t ipv6_address1 Offset of IPv6 address 1.

◆ layer3_switch_frame_vlan_tag_t

struct layer3_switch_frame_vlan_tag_t

VLAN tag structre.

Data Fields
uint16_t pcp: 3 Priority Code Point (3 bit).
uint16_t dei: 1 Drop Eligible Indicator (1 bit).
uint16_t id: 12 VLAN ID (12 bit).

◆ layer3_switch_frame_filter_t

struct layer3_switch_frame_filter_t

Frame filter of a MAC/VLAN/Layer3 forwarding entry. Set values for members required for filtering.

Data Fields
layer3_switch_table_entry_type_t entry_type Type of this entry. Selcet MAC, VLAN or Layer3.
uint8_t * p_destination_mac_address Destination MAC address.
uint8_t * p_source_mac_address Source MAC address.
layer3_switch_frame_vlan_tag_t vlan_c_tag VLAN C-TAG.
layer3_switch_frame_vlan_tag_t vlan_s_tag VLAN S-TAG.
layer3_switch_ip_version_t ip_version IP version. Select IPv4, IPv6, or not IP packet.
uint8_t protocol IP protocol.
uint8_t * p_source_ip_address Source IP address.
uint8_t * p_destination_ip_address Destination IP address.
uint16_t layer4_source_port TCP/UDP source port.
uint16_t layer4_destination_port TCP/UDP destination port.

◆ layer3_switch_l3_filter_t

struct layer3_switch_l3_filter_t

Store filter information of Layer3 forwarding entry.

Data Fields
layer3_switch_frame_filter_t frame Target frame format that used to Layer3 forwarding.

◆ layer3_switch_l3_update_config_t

struct layer3_switch_l3_update_config_t

Configuration of a L2/L3 update feature for output frames.

Data Fields
uint32_t enable_destination_ports Destination ports that this update config is enabled.
uint32_t update_field_bitmask Bit mask of which fields will be updated. Use layer3_switch_l3_update_bitmask_t.
uint8_t * p_mac_destination_address MAC Destination Address.
layer3_switch_frame_vlan_tag_t vlan_c_tag VLAN C-tag.
layer3_switch_frame_vlan_tag_t vlan_s_tag VLAN S-tag.
layer3_switch_forwarding_r_tag_t r_tag_update_mode R-TAG update setting.

◆ layer3_switch_table_entry_cfg_t

struct layer3_switch_table_entry_cfg_t

Table entry configuration of MAC/VLAN/Layer3 forwarding.

Data Fields
bool entry_enable Enable or disable entry. If this field is false, entry will be removed.
bool security_enable Entry is secure or not.
uint32_t destination_ports Destination ports of forwarding.
uint32_t source_ports Source ports that enable forwarding of incoming frame.
uint32_t destination_queue_index Destination queue. This fields is only used when a destination port is CPU.
uint32_t internal_priority_update_enable Enable to update internal priority.
uint32_t internal_priority_update_value Internal priority when updating is enabled.
union layer3_switch_table_entry_cfg_t __unnamed__

◆ layer3_switch_table_entry_t

struct layer3_switch_table_entry_t

Table entry of MAC/VLAN/Layer3 forwarding.

Data Fields
layer3_switch_frame_filter_t target_frame Target frame of forwarding by this entry.
layer3_switch_table_entry_cfg_t entry_cfg Configuration of this entry.

◆ layer3_switch_forwarding_port_cfg_t

struct layer3_switch_forwarding_port_cfg_t

Configuration of forwarding feature for each port.

Data Fields
bool mac_table_enable Enable MAC table and forwarding feature.
bool mac_reject_unknown Reject frame with unknown MAC address.
bool mac_hardware_learning_enable Enable hardware learning and migration.
bool vlan_table_enable Enable VLAN table and forwarding feature.
bool vlan_reject_unknown Reject frame with unknown VLAN ID.
layer3_switch_vlan_ingress_mode_t vlan_ingress_mode Select Tag-based VLAN or Port-based VLAN for incoming frame.
layer3_switch_vlan_egress_mode_t vlan_egress_mode Tagging/untagging mode for outgoing frame.
layer3_switch_frame_vlan_tag_t vlan_s_tag S-TAG of this port. When egress mode is hardware SC-TAG, add this to outgoing frame.
layer3_switch_frame_vlan_tag_t vlan_c_tag C-TAG of this port. When egress mode is hardware C-TAG, add this to outgoing frame.
bool layer3_table_enable Enable Layer3 table and forwarding feature.
bool layer3_reject_unknown Reject frame that not found in Layer3 table.
bool layer3_ipv4_filter_enable Enable IPv4 stream filter.
bool layer3_ipv6_filter_enable Enable IPv6 stream filter.
bool layer3_l2_filter_enable Enable L2 stream filter.

◆ layer3_switch_table_t

struct layer3_switch_table_t

Forwarding table containing MAC/VLAN/Layer3 forwarding entries.

Data Fields
layer3_switch_table_entry_t * p_mac_entry_list List of MAC entries.
uint32_t mac_list_length Length of the MAC entry list.
layer3_switch_table_entry_t * p_vlan_entry_list List of VLAN entries.
uint32_t vlan_list_length Length of the VLAN entry list.
layer3_switch_table_entry_t * p_l3_entry_list List of Layer3 entries.
uint32_t l3_list_length Length of the Layer3 entry list.

◆ layer3_switch_table_cfg_t

struct layer3_switch_table_cfg_t

Configuration of the forwarding table.

Data Fields
layer3_switch_table_t * p_table Pointer to forwarding table.
layer3_switch_forwarding_port_cfg_t port_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS+1] Forwarding configuration of each port.
uint32_t unsecure_entry_maximum_num Maximum number of unsecure entries.
bool mac_entry_aging_enable Enable aging feature of MAC table.
uint32_t mac_entry_aging_time_sec Time[s] to delete an entry by aging.
layer3_switch_vlan_mode_t vlan_mode VLAN mode options: NO VLAN, C-TAG, or SC-TAG.
layer3_switch_l3_stream_filter_cfg_t l3_stream_filter_cfg Configuration of stream filter in Layer3 forwarding.

◆ layer3_switch_extended_cfg_t

struct layer3_switch_extended_cfg_t

ESWM extension configures each Ethernet port and forwarding feature.

Data Fields
ether_phy_instance_t const * p_ether_phy_instances[BSP_FEATURE_ETHER_NUM_CHANNELS] List of pointers to ETHER_PHY instance.
gptp_instance_t const * p_gptp_instance Pointer to a gPTP instance.
uint32_t fowarding_target_port_masks[BSP_FEATURE_ETHER_NUM_CHANNELS] List of ports to which incoming frames are forwarded.
uint8_t * p_mac_addresses[BSP_FEATURE_ETHER_NUM_CHANNELS]
uint32_t ipv_queue_depth_list[BSP_FEATURE_ETHER_NUM_CHANNELS][8] List of IPV queue depth for each port.
layer3_switch_l3_filter_t * l3_filter_list Filter list of layer3 routing.
uint32_t l3_filter_list_length Length of Layer3 filter list.
layer3_switch_port_cfg_t * p_port_cfg_list[BSP_FEATURE_ETHER_NUM_CHANNELS] Configuration for each port.
IRQn_Type etha_error_irq_port_0 ETHA error interrupt number for port 0.
IRQn_Type etha_error_irq_port_1 ETHA error interrupt number for port 1.
uint8_t etha_error_ipl_port_0 ETHA error interrupt priorirty for port 0.
uint8_t etha_error_ipl_port_1 ETHA error interrupt priorirty for port 1.

◆ layer3_switch_instance_ctrl_t

struct layer3_switch_instance_ctrl_t

LAYER3_SWITCH control block. DO NOT INITIALIZE. Initialization occurs when ether_switch_api_t::open is called.

Data Fields

uint32_t open
 Used to determine if the channel is configured.
 
ether_switch_cfg_t const * p_cfg
 Pointer to initial configurations.
 
R_GWCA0_Type * p_gwca_reg
 Pointer to GWCA register.
 
uint32_t allocated_descriptor_queue_index
 Index of the descriptor pool.
 
layer3_switch_basic_descriptor_t p_descriptor_queue_list [LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM]
 Descriptor queue lists used by hardware.
 
layer3_switch_descriptor_queue_status_t p_queues_status [LAYER3_SWITCH_CFG_AVAILABLE_QUEUE_NUM]
 Status of each descriptor queues.
 
layer3_switch_port_cfg_t p_port_cfg_list [BSP_FEATURE_ETHER_NUM_CHANNELS]
 Configuration for each port.
 
layer3_switch_table_status_t table_status
 Forwarding table is initialized or not.
 
uint32_t l3_entry_count
 Counts of valid LAYER3 entry.
 
uint8_t l3_routing_number
 Routing number for L2/L3 update feature.
 
uint8_t l3_remapping_number
 Remapping number for L2/L3 update feature.
 
void(* p_callback )(ether_switch_callback_args_t *p_args)
 Callback provided when an ISR occurs.
 
ether_switch_callback_args_t * p_callback_memory
 Pointer to optional callback argument memory.
 
void * p_context
 Pointer to context to be passed into callback function.
 

◆ layer3_switch_tas_entry_t

struct layer3_switch_tas_entry_t

Configuration of the gate operation.

Data Fields
layer3_switch_tas_gate_state_t state Gate state.
uint32_t time Time associated with the entry gate state [nsec].

◆ layer3_switch_tas_gate_cfg_t

struct layer3_switch_tas_gate_cfg_t

Configuration of the gate.

Data Fields
layer3_switch_tas_gate_state_t initial_gate_state Initial gate state when the cycle starts.
uint8_t tas_entry_num Number of TAS entries included in this gate.
layer3_switch_tas_entry_t * p_tas_entry_list List of TAS entries included in this gate.

◆ layer3_switch_tas_cfg_t

struct layer3_switch_tas_cfg_t

Configuration of the TAS.

Data Fields
uint8_t gptp_timer_number gPTP timer number.
uint32_t cycle_time_start_high Upper 32 bits of TAS cycle start time [nsec].
uint32_t cycle_time_start_low Lower 32 bits of TAS cycle start time [nsec].
uint32_t cycle_time TAS cycle time [nsec].
layer3_switch_tas_gate_cfg_t gate_cfg_list[8] List of TAS gate configurations.

Enumeration Type Documentation

◆ layer3_switch_descriptor_type_t

enum layer3_switch_descriptor_type_t

GWCA descriptor type.

Enumerator
LAYER3_SWITCH_DESCRIPTOR_TYPE_LINKFIX 

Linkfix. Control element pointing to next descriptor in chain.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_IS 

Frame Empty Incremental Start.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_IC 

Frame Empty Incremental Continue.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_ND 

Frame Empty No Data Storage.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY 

Frame Empty.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_START 

Frame Empty Start.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_MID 

Frame Empty Mid.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEMPTY_END 

Frame Empty End.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FSINGLE 

Frame Single.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FSTART 

Frame Start.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FMID 

Frame Mid.

LAYER3_SWITCH_DESCRIPTOR_TYPE_FEND 

Frame End.

LAYER3_SWITCH_DESCRIPTOR_TYPE_LEMPTY 

Link Empty.

LAYER3_SWITCH_DESCRIPTOR_TYPE_EEMPTY 

EOS Empty.

LAYER3_SWITCH_DESCRIPTOR_TYPE_LINK 

Link.

LAYER3_SWITCH_DESCRIPTOR_TYPE_EOS 

End of Set.

◆ layer3_switch_port_bitmask_t

enum layer3_switch_port_bitmask_t

Bitmasks for each port.

Enumerator
LAYER3_SWITCH_PORT_BITMASK_PORT0 

Port 0.

LAYER3_SWITCH_PORT_BITMASK_PORT1 

Port 1.

LAYER3_SWITCH_PORT_BITMASK_PORT2 

Port 2.

◆ layer3_switch_queue_type_t

enum layer3_switch_queue_type_t

Descriptor queue type.

Enumerator
LAYER3_SWITCH_QUEUE_TYPE_RX 

Reception queue.

LAYER3_SWITCH_QUEUE_TYPE_TX 

Transmission queue.

◆ layer3_switch_descriptor_format_t

enum layer3_switch_descriptor_format_t

Descriptor format type.

Enumerator
LAYER3_SWITCH_DISCRIPTOR_FORMTAT_BASIC 

Using basic descriptor.

LAYER3_SWITCH_DISCRIPTOR_FORMTAT_EXTENDED 

Using extended descriptor with additional fields.

◆ layer3_switch_write_back_mode_t

enum layer3_switch_write_back_mode_t

Write back mode.

Enumerator
LAYER3_SWITCH_WRITE_BACK_MODE_FULL 

All fields are updated by hardware.

LAYER3_SWITCH_WRITE_BACK_MODE_DISABLE 

No fields are updated by hardware.

LAYER3_SWITCH_WRITE_BACK_MODE_KEEP_DT 

Fields exclude DT are updated by hardware.

◆ layer3_switch_ip_version_t

enum layer3_switch_ip_version_t

IP version options.

Enumerator
LAYER3_SWITCH_IP_VERSION_NONE 

Not IP packet.

LAYER3_SWITCH_IP_VERSION_IPV4 

IPv4 packet.

LAYER3_SWITCH_IP_VERSION_IPV6 

IPv6 packet.

◆ layer3_switch_ip_address_direction_t

enum layer3_switch_ip_address_direction_t

Direction of IP address.

Enumerator
LAYER3_SWITCH_IP_ADDRESS_DIRECTION_SOURCE 

Use IP source address in stream ID.

LAYER3_SWITCH_IP_ADDRESS_DIRECTION_DESTINATION 

Use IP destination address in stream ID.

◆ layer3_switch_magic_packet_detection_t

enum layer3_switch_magic_packet_detection_t

Magic packet detection options.

Enumerator
LAYER3_SWITCH_MAGIC_PACKET_DETECTION_ENABLE 

Enable magic packet detection.

LAYER3_SWITCH_MAGIC_PACKET_DETECTION_DISABLE 

Disable magic packet detection.

◆ layer3_switch_vlan_mode_t

enum layer3_switch_vlan_mode_t

VLAN detection mode.

Enumerator
LAYER3_SWITCH_VLAN_MODE_NO_VLAN 

Not use VLAN feature.

LAYER3_SWITCH_VLAN_MODE_C_TAG 

Detect and use VLAN C-TAG.

LAYER3_SWITCH_VLAN_MODE_SC_TAG 

Detect and use VLAN SC-TAG.

◆ layer3_switch_vlan_ingress_mode_t

enum layer3_switch_vlan_ingress_mode_t

VLAN ingress mode determines whether the switch operates with tagged VLAN or port-based VLAN.

Enumerator
LAYER3_SWITCH_VLAN_INGRESS_MODE_TAG_BASED 

Use VLAN ID of the incoming frame.

LAYER3_SWITCH_VLAN_INGRESS_MODE_PORT_BASED 

Use VLAN ID of the incoming port.

◆ layer3_switch_vlan_egress_mode_t

enum layer3_switch_vlan_egress_mode_t

VLAN egress mode determines the VLAN tag that is added to output frames.

Enumerator
LAYER3_SWITCH_VLAN_EGRESS_MODE_NO_VLAN 

Frame always outgoing without VLAN TAG.

LAYER3_SWITCH_VLAN_EGRESS_MODE_C_TAG 

Frame outgoing with C-TAG of incoming frame.

LAYER3_SWITCH_VLAN_EGRESS_MODE_HW_C_TAG 

Frame always outgoing with C-TAG of output port.

LAYER3_SWITCH_VLAN_EGRESS_MODE_SC_TAG 

Frame always outgoing with SC-TAG of incoming frame.

LAYER3_SWITCH_VLAN_EGRESS_MODE_HW_SC_TAG 

Frame always outgoing with SC-TAG of output port.

◆ layer3_switch_ip_protocol_t

enum layer3_switch_ip_protocol_t

IP protocols type.

Enumerator
LAYER3_SWITCH_IP_PROTOCOL_TCP 

IP protocol is TCP.

LAYER3_SWITCH_IP_PROTOCOL_UDP 

IP protocol is UDP.

◆ layer3_switch_forwarding_r_tag_t

enum layer3_switch_forwarding_r_tag_t

R-TAG filed update options.

Enumerator
LAYER3_SWITCH_FORWARDING_R_TAG_UPDATE 

Incoming frame with R-TAG will be updated with new R-TAG.

LAYER3_SWITCH_FORWARDING_R_TAG_ALWAYS_ADD 

ALl incoming frame will be added new R-TAG.

LAYER3_SWITCH_FORWARDING_R_TAG_ALWAYS_ELIMINATE 

ALl incoming frame will be removed R-TAG.

◆ layer3_switch_l3_filter_bitmask_t

enum layer3_switch_l3_filter_bitmask_t

Frame filters options for layer3 forwarding.

Enumerator
LAYER3_SWITCH_L3_FILTER_BITMASK_MAC_DESTINATION 

Enable MAC destination address.

LAYER3_SWITCH_L3_FILTER_BITMASK_MAC_SOURCE 

Enable MAC source address.

LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_ID 

Enable VLAN ID of S-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_PCP 

Enable PCP of S-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_STAG_DEI 

Enable DEI of S-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_ID 

Enable VLAN ID of C-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_PCP 

Enable PCP of C-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_CTAG_DEI 

Enable DEI of C-TAG.

LAYER3_SWITCH_L3_FILTER_BITMASK_IP_SOURCE_ADDRESS 

Enable IP source address.

LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_ADDRESS 

Enable IP destination address.

LAYER3_SWITCH_L3_FILTER_BITMASK_PROTOCOL 

Enable IP protocol.

LAYER3_SWITCH_L3_FILTER_BITMASK_IP_SOURCE_PORT 

Enable layer4 source port.

LAYER3_SWITCH_L3_FILTER_BITMASK_IP_DESTINATION_PORT 

Enable layer4 destination port.

◆ layer3_switch_l3_update_bitmask_t

enum layer3_switch_l3_update_bitmask_t

Enable L2/L3 update feature.

Enumerator
LAYER3_SWITCH_L3_UPDATE_BITMASK_TTL 

Update TTL.

LAYER3_SWITCH_L3_UPDATE_BITMASK_MAC_DESTINATION 

Update MAC destination address.

LAYER3_SWITCH_L3_UPDATE_BITMASK_MAC_SOURCE 

Update MAC source address.

LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_ID 

Update VLAN ID of C-TAG.

LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_PCP 

Update PCP of C-TAG.

LAYER3_SWITCH_L3_UPDATE_BITMASK_CTAG_DEI 

Update DEI of C-TAG.

LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_ID 

Update VLAN ID of C-TAG.

LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_PCP 

Update PCP of C-TAG.

LAYER3_SWITCH_L3_UPDATE_BITMASK_STAG_DEI 

Update DEI of C-TAG.

◆ layer3_switch_table_entry_type_t

enum layer3_switch_table_entry_type_t

Table entry type for forwarding feature.

Enumerator
LAYER3_SWITCH_TABLE_ENTRY_TYPE_EMPTY 

Entry is not initialized yet.

LAYER3_SWITCH_TABLE_ENTRY_TYPE_MAC 

Entry of MAC table.

LAYER3_SWITCH_TABLE_ENTRY_TYPE_VLAN 

Entry of VLAN table.

LAYER3_SWITCH_TABLE_ENTRY_TYPE_LAYER3 

Entry of Layer3 table.

◆ layer3_switch_table_status_t

enum layer3_switch_table_status_t

Table status for forwarding feature.

Enumerator
LAYER3_SWITCH_TABLE_STATUS_UNINITIALIZED 

Forwarding table is uninitialized.

LAYER3_SWITCH_TABLE_STATUS_INITIALIZED 

Forwarding table is initialized.

◆ layer3_switch_tas_gate_state_t

enum layer3_switch_tas_gate_state_t

TAS gate state.

Enumerator
LAYER3_SWITCH_TAS_GATE_STATE_CLOSE 

Gate is closed.

LAYER3_SWITCH_TAS_GATE_STATE_OPEN 

Gate is opened.

Function Documentation

◆ R_LAYER3_SWITCH_Open()

fsp_err_t R_LAYER3_SWITCH_Open ( ether_switch_ctrl_t *const  p_ctrl,
ether_switch_cfg_t const *const  p_cfg 
)

Initializes the switch module and applies configurations. Implements ether_switch_api_t::open.

Return values
FSP_SUCCESSChannel opened successfully.
FSP_ERR_ASSERTIONPointer to control block, config structure or extended config structure is NULL.
FSP_ERR_ALREADY_OPENControl block has already been opened or channel is being used by another instance. Call close() then open() to reconfigure.
FSP_ERR_ETHER_ERROR_PHY_COMMUNICATIONInitialization of PHY-LSI failed.
FSP_ERR_INVALID_ARGUMENTInvalid configuration value.

◆ R_LAYER3_SWITCH_Close()

fsp_err_t R_LAYER3_SWITCH_Close ( ether_switch_ctrl_t *const  p_ctrl)

Disables interrupts and stop module. Implements ether_switch_api_t::close.

Return values
FSP_SUCCESSChannel successfully closed.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENControl block is not open.

◆ R_LAYER3_SWITCH_CreateDescriptorQueue()

fsp_err_t R_LAYER3_SWITCH_CreateDescriptorQueue ( ether_switch_ctrl_t *const  p_ctrl,
uint32_t *const  p_queue_index,
const layer3_switch_descriptor_queue_cfg_t *const  p_queue_cfg 
)

Create a new descriptor queue and set it to LINKFIX table. This function must be called before calling R_LAYER3_SWITCH_SetDescriptor and R_LAYER3_SWITCH_GetDescriptor.

Return values
FSP_SUCCESSDescipritor created successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENControl block is not open.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_OUT_OF_MEMORYDescriptor queue list is depleted.

◆ R_LAYER3_SWITCH_SetDescriptor()

fsp_err_t R_LAYER3_SWITCH_SetDescriptor ( ether_switch_ctrl_t *const  p_ctrl,
uint32_t  queue_index,
const layer3_switch_descriptor_t *const  p_descriptor 
)

Set descripotor data to a target descriptor.

Return values
FSP_SUCCESSDescriptor set successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENControl block is not open.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_INVALID_ARGUMENTQueue index is invalid.
FSP_ERR_NOT_INITIALIZEDThis descriptor queue is not created.
FSP_ERR_IN_USETarget descriptor is now running.
FSP_ERR_OVERFLOWDescriptor queue is full.

◆ R_LAYER3_SWITCH_GetDescriptor()

fsp_err_t R_LAYER3_SWITCH_GetDescriptor ( ether_switch_ctrl_t *const  p_ctrl,
uint32_t  queue_index,
layer3_switch_descriptor_t *const  p_descriptor 
)

Get descripotor data from a target descriptor.

Return values
FSP_SUCCESSDescriptor got successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENControl block is not open.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_INVALID_ARGUMENTQueue index is invalid.
FSP_ERR_NOT_INITIALIZEDThis descriptor queue is not created or target descriptor is not set.
FSP_ERR_IN_USETarget descriptor is now running.

◆ R_LAYER3_SWITCH_StartDescriptorQueue()

fsp_err_t R_LAYER3_SWITCH_StartDescriptorQueue ( ether_switch_ctrl_t *const  p_ctrl,
uint32_t  queue_index 
)

Reload and enable a descriptor queue. In a TX descriptor queue, the queue start transmission. In a RX descriptor queue, the queue start reception.

Return values
FSP_SUCCESSDescriptor queue started successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENControl block is not open.
FSP_ERR_INVALID_ARGUMENTQueue index is invalid.
FSP_ERR_NOT_INITIALIZEDTarget descriptor queue is not created.
FSP_ERR_IN_USETarget descriptor queue is already running.

◆ R_LAYER3_SWITCH_CallbackSet()

fsp_err_t R_LAYER3_SWITCH_CallbackSet ( ether_switch_ctrl_t *const  p_ctrl,
void(*)(ether_switch_callback_args_t *)  p_callback,
void *const  p_context,
ether_switch_callback_args_t *const  p_callback_memory 
)

Updates the user callback with the option to provide memory for the callback argument structure.

Return values
FSP_SUCCESSCallback updated successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_NO_CALLBACK_MEMORYp_callback is non-secure and p_callback_memory is either secure or NULL.

◆ R_LAYER3_SWITCH_ConfigurePort()

fsp_err_t R_LAYER3_SWITCH_ConfigurePort ( ether_switch_ctrl_t *const  p_ctrl,
uint8_t  port,
layer3_switch_port_cfg_t *  p_port_cfg 
)

Configure Ethernet port features, including callback function for each port.

Return values
FSP_SUCCESSPort configured successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL..
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_INVALID_ARGUMENTPort number is invalid.

◆ R_LAYER3_SWITCH_AddTableEntry()

fsp_err_t R_LAYER3_SWITCH_AddTableEntry ( ether_switch_ctrl_t *const  p_ctrl,
layer3_switch_frame_filter_t const *const  p_target_frame,
layer3_switch_table_entry_cfg_t const *const  p_entry_cfg 
)

Add or update an entry of the forwarding table.

Return values
FSP_SUCCESSSuccessfully add/updated an entry into the table.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_OVERFLOWThe number of unsecure entries exceeded the configured value.
FSP_ERR_WRITE_FAILEDA hardware error occurred while learning the entry.
FSP_ERR_INVALID_ARGUMENTTarget frame or entry type is invalid.
FSP_ERR_INVALID_MODEVLAN feature is disabled and a VLAN entry is passed.

◆ R_LAYER3_SWITCH_SearchTableEntry()

fsp_err_t R_LAYER3_SWITCH_SearchTableEntry ( ether_switch_ctrl_t *const  p_ctrl,
layer3_switch_frame_filter_t const *const  p_target_frame,
layer3_switch_table_entry_cfg_t *const  p_entry_cfg 
)

Search an entry from the forwarding table.

Return values
FSP_SUCCESSThe entry is found successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_NOT_FOUNDThe entry is not found in the table.
FSP_ERR_INVALID_ARGUMENTTarget frame or entry type is invalid.
FSP_ERR_INVALID_MODEVLAN feature is disabled and a VLAN entry is passed.

◆ R_LAYER3_SWITCH_ConfigureTable()

fsp_err_t R_LAYER3_SWITCH_ConfigureTable ( ether_switch_ctrl_t *const  p_ctrl,
layer3_switch_table_cfg_t const *const  p_table_cfg 
)

Configure and initailze an forwarding table.

Return values
FSP_SUCCESSTable configured successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_WRITE_FAILEDFailed to add entries.

◆ R_LAYER3_SWITCH_GetTable()

fsp_err_t R_LAYER3_SWITCH_GetTable ( ether_switch_ctrl_t *const  p_ctrl,
layer3_switch_table_t *const  p_table 
)

Get a pointer to the forwarding table.

Return values
FSP_SUCCESSTable got successfully.
FSP_ERR_ASSERTIONPointer to control block is NULL.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_INVALID_MODEVLAN feature is disabled and a VLAN entry list is passed.

◆ R_LAYER3_SWITCH_ConfigureTAS()

fsp_err_t R_LAYER3_SWITCH_ConfigureTAS ( ether_switch_ctrl_t *const  p_ctrl,
uint8_t  port,
layer3_switch_tas_cfg_t *  p_tas_cfg 
)

Configure Time Aware Shaper feature.

Return values
FSP_SUCCESSTAS configure successfully.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_POINTERPointer to a argument is NULL.
FSP_ERR_INVALID_ARGUMENTPort number is invalid.
FSP_ERR_UNSUPPORTEDTAS feature is not enabled in the configuration.

◆ R_LAYER3_SWITCH_EnableTAS()

fsp_err_t R_LAYER3_SWITCH_EnableTAS ( ether_switch_ctrl_t *const  p_ctrl,
uint8_t  port 
)

Enable Time Aware Shaper feature.

Return values
FSP_SUCCESSTAS enabled successfully.
FSP_ERR_NOT_OPENThe control block has not been opened.
FSP_ERR_INVALID_ARGUMENTPort number is invalid.
FSP_ERR_UNSUPPORTEDTAS feature is not enabled in the configuration.