RZG Namespace Reference

Classes
struct	iic_master_clock_settings
struct	iic_slave_clock_settings
struct	s_gpt_gtior_setting
struct	s_gpt_output_pin
struct	s_i3c_b_bitrate_settings
struct	s_i3c_b_clock_stalling
struct	s_i3c_b_extended_cfg
struct	s_i3c_b_ibi_control
struct	s_i3c_b_read_buffer_descriptor
struct	s_i3c_b_slave_command_response_info
struct	s_i3c_b_write_buffer_descriptor
struct	s_i3c_callback_args
struct	s_i3c_command_descriptor
struct	s_i3c_device_status
struct	s_i3c_device_table_cfg
struct	s_i3c_slave_device_cfg
struct	s_i3c_slave_info
struct	st_adc_api
struct	st_adc_c_channel_cfg
struct	st_adc_c_extended_cfg
struct	st_adc_c_instance_ctrl
struct	st_adc_callback_args
struct	st_adc_cfg
struct	st_adc_e_channel_cfg
struct	st_adc_e_extended_cfg
struct	st_adc_e_instance_ctrl
struct	st_adc_e_window_cfg
struct	st_adc_info
struct	st_adc_instance
struct	st_adc_status
struct	st_baud_setting
struct	st_can_api
struct	st_can_bit_timing_cfg
struct	st_can_callback_args
struct	st_can_cfg
struct	st_can_frame
struct	st_can_info
struct	st_can_instance
struct	st_canfd_afl_entry
struct	st_canfd_extended_cfg
struct	st_canfd_global_cfg
struct	st_canfd_instance_ctrl
struct	st_cmtw_extended_cfg
struct	st_cmtw_instance_ctrl
struct	st_crc_api
struct	st_crc_cfg
struct	st_crc_extended_cfg
struct	st_crc_input_t
struct	st_crc_instance
struct	st_crc_instance_ctrl
struct	st_dmac_b_extended_cfg
struct	st_dmac_b_extended_info
struct	st_dmac_b_instance_ctrl
struct	st_dmac_b_link_cfg
struct	st_dmac_b_register_set_setting_t
struct	st_elc_api
struct	st_elc_cfg
struct	st_elc_instance
struct	st_elc_instance_ctrl
struct	st_external_irq_api
struct	st_external_irq_callback_args
struct	st_external_irq_cfg
struct	st_external_irq_instance
union	st_fsp_pack_version
struct	st_gpt_extended_cfg
struct	st_gpt_extended_pwm_cfg
struct	st_gpt_instance_ctrl
struct	st_gtm_extended_cfg
struct	st_gtm_instance_ctrl
struct	st_i2c_master_api
struct	st_i2c_master_callback_args
struct	st_i2c_master_cfg
struct	st_i2c_master_instance
struct	st_i2c_master_status
struct	st_i2c_slave_api
struct	st_i2c_slave_callback_args
struct	st_i2c_slave_cfg
struct	st_i2c_slave_instance
struct	st_i3c_api
struct	st_i3c_b_instance_ctrl
struct	st_i3c_cfg
struct	st_i3c_instance
struct	st_iic_master_instance_ctrl
struct	st_iic_slave_instance_ctrl
struct	st_intc_irq_instance_ctrl
struct	st_intc_nmi_instance_ctrl
struct	st_intc_tint_extended_cfg
struct	st_intc_tint_instance_ctrl
struct	st_ioport_api
struct	st_ioport_cfg
struct	st_ioport_event_group_input
struct	st_ioport_event_group_output
struct	st_ioport_event_single
struct	st_ioport_extend_cfg
struct	st_ioport_instance
struct	st_ioport_instance_ctrl
struct	st_ioport_pin_cfg
struct	st_mhu_api
struct	st_mhu_b_ns_extended_cfg
struct	st_mhu_b_ns_instance_ctrl
struct	st_mhu_b_ns_swint_get_extended_cfg
struct	st_mhu_b_ns_swint_get_instance_ctrl
struct	st_mhu_b_ns_swint_set_extended_cfg
struct	st_mhu_b_ns_swint_set_instance_ctrl
struct	st_mhu_b_s_extended_cfg
struct	st_mhu_b_s_instance_ctrl
struct	st_mhu_callback_args
struct	st_mhu_cfg
struct	st_mhu_instance
struct	st_mhu_ns_extended_cfg
struct	st_mhu_ns_instance_ctrl
struct	st_mhu_ns_swint_get_api
struct	st_mhu_ns_swint_get_callback_args
struct	st_mhu_ns_swint_get_cfg
struct	st_mhu_ns_swint_get_extended_cfg
struct	st_mhu_ns_swint_get_instance
struct	st_mhu_ns_swint_get_instance_ctrl
struct	st_mhu_ns_swint_set_api
struct	st_mhu_ns_swint_set_callback_args
struct	st_mhu_ns_swint_set_cfg
struct	st_mhu_ns_swint_set_extended_cfg
struct	st_mhu_ns_swint_set_instance
struct	st_mhu_ns_swint_set_instance_ctrl
struct	st_mhu_s_extended_cfg
struct	st_mhu_s_instance_ctrl
struct	st_mtu3_extended_cfg
struct	st_mtu3_extended_pwm_cfg
struct	st_mtu3_instance_ctrl
struct	st_mtu3_output_pin
struct	st_pdm_api
struct	st_pdm_callback_args
struct	st_pdm_cfg
struct	st_pdm_extended_cfg
struct	st_pdm_instance
struct	st_pdm_instance_ctrl
struct	st_pdm_sound_detection_setting
struct	st_pdm_status
struct	st_poeg_api
struct	st_poeg_callback_args
struct	st_poeg_cfg
struct	st_poeg_extended_cfg
struct	st_poeg_instance
struct	st_poeg_instance_ctrl
struct	st_poeg_status
struct	st_qspi_timing_setting
struct	st_riic_master_extended_cfg
struct	st_riic_slave_extended_cfg
struct	st_rm_comms_api
struct	st_rm_comms_callback_args
struct	st_rm_comms_cfg
struct	st_rm_comms_i2c_bus_extended_cfg
struct	st_rm_comms_i2c_instance_ctrl
struct	st_rm_comms_instance
struct	st_rm_comms_write_read_params
struct	st_rspck_div_setting
struct	st_rspi_extended_cfg
struct	st_rspi_instance_ctrl
struct	st_rspi_rspck_div_setting
struct	st_rtc_alarm_time
struct	st_rtc_api
struct	st_rtc_callback_args
struct	st_rtc_cfg
struct	st_rtc_ctrl
struct	st_rtc_error_adjustment_cfg
struct	st_rtc_extended_cfg
struct	st_rtc_info
struct	st_rtc_instance
struct	st_rtc_time_capture
struct	st_sci_b_baud_setting_t
struct	st_sci_b_i2c_clock_settings
struct	st_sci_b_i2c_extended_cfg
struct	st_sci_b_i2c_instance_ctrl
struct	st_sci_b_spi_div_setting
struct	st_sci_b_spi_extended_cfg
struct	st_sci_b_spi_instance_ctrl
struct	st_sci_b_uart_extended_cfg
struct	st_sci_b_uart_instance_ctrl
struct	st_sci_b_uart_rs485_setting
struct	st_sci_b_uart_sci_b_uart_half_data_setting
struct	st_sci_uart_extended_cfg
struct	st_sci_uart_instance_ctrl
struct	st_sci_uart_rs485_setting
struct	st_scif_baud_setting
struct	st_scif_uart_extended_cfg
struct	st_scif_uart_instance_ctrl
struct	st_scif_uart_rs485_setting
struct	st_spi_api
struct	st_spi_b_extended_cfg
struct	st_spi_b_instance_ctrl
struct	st_spi_callback_args
struct	st_spi_cfg
struct	st_spi_flash_api
struct	st_spi_flash_cfg
struct	st_spi_flash_direct_transfer
struct	st_spi_flash_erase_command
struct	st_spi_flash_instance
struct	st_spi_flash_status
struct	st_spi_instance
struct	st_spi_write_read_guard_args
struct	st_timer_api
struct	st_timer_callback_args
struct	st_timer_cfg
struct	st_timer_info
struct	st_timer_instance
struct	st_timer_status
struct	st_transfer_api
struct	st_transfer_callback_args_t
struct	st_transfer_cfg
struct	st_transfer_info
struct	st_transfer_instance
struct	st_transfer_properties
struct	st_tsu_b_extended_cfg
struct	st_tsu_b_instance_ctrl
struct	st_uart_api
struct	st_uart_callback_arg
struct	st_uart_cfg
struct	st_uart_info
struct	st_uart_instance
struct	st_wdt_api
struct	st_wdt_callback_args
struct	st_wdt_cfg
struct	st_wdt_extended_cfg
struct	st_wdt_instance
struct	st_wdt_instance_ctrl
struct	st_wdt_timeout_values
struct	st_xspi_qspi_extended_cfg
struct	st_xspi_qspi_instance_ctrl

Typedefs
typedef struct st_adc_status	adc_status_t
typedef struct st_adc_callback_args	adc_callback_args_t
typedef struct st_adc_info	adc_info_t
typedef struct st_adc_cfg	adc_cfg_t
typedef void	adc_ctrl_t
typedef struct st_adc_api	adc_api_t
typedef struct st_adc_instance	adc_instance_t
typedef struct st_can_info	can_info_t
typedef struct st_can_bit_timing_cfg	can_bit_timing_cfg_t
typedef struct st_can_frame	can_frame_t
typedef struct st_can_callback_args	can_callback_args_t
typedef struct st_can_cfg	can_cfg_t
typedef void	can_ctrl_t
typedef struct st_can_api	can_api_t
typedef struct st_can_instance	can_instance_t
typedef struct st_crc_input_t	crc_input_t
typedef void	crc_ctrl_t
typedef struct st_crc_cfg	crc_cfg_t
typedef struct st_crc_api	crc_api_t
typedef struct st_crc_instance	crc_instance_t
typedef void	elc_ctrl_t
typedef struct st_elc_cfg	elc_cfg_t
typedef struct st_elc_api	elc_api_t
typedef struct st_elc_instance	elc_instance_t
typedef struct st_external_irq_callback_args	external_irq_callback_args_t
typedef struct st_external_irq_cfg	external_irq_cfg_t
typedef void	external_irq_ctrl_t
typedef struct st_external_irq_api	external_irq_api_t
typedef struct st_external_irq_instance	external_irq_instance_t
typedef struct st_i2c_master_callback_args	i2c_master_callback_args_t
typedef struct st_i2c_master_status	i2c_master_status_t
typedef struct st_i2c_master_cfg	i2c_master_cfg_t
typedef void	i2c_master_ctrl_t
typedef struct st_i2c_master_api	i2c_master_api_t
typedef struct st_i2c_master_instance	i2c_master_instance_t
typedef struct st_i2c_slave_callback_args	i2c_slave_callback_args_t
typedef struct st_i2c_slave_cfg	i2c_slave_cfg_t
typedef void	i2c_slave_ctrl_t
typedef struct st_i2c_slave_api	i2c_slave_api_t
typedef struct st_i2c_slave_instance	i2c_slave_instance_t
typedef struct s_i3c_device_status	i3c_device_status_t
typedef struct s_i3c_slave_info	i3c_slave_info_t
typedef struct s_i3c_device_table_cfg	i3c_device_table_cfg_t
typedef struct s_i3c_slave_device_cfg	i3c_device_cfg_t
typedef struct s_i3c_command_descriptor	i3c_command_descriptor_t
typedef struct s_i3c_callback_args	i3c_callback_args_t
typedef struct st_i3c_cfg	i3c_cfg_t
typedef void	i3c_ctrl_t
typedef struct st_i3c_api	i3c_api_t
typedef struct st_i3c_instance	i3c_instance_t
typedef uint16_t	ioport_size_t
	IO port size. More...
typedef struct st_ioport_pin_cfg	ioport_pin_cfg_t
typedef struct st_ioport_cfg	ioport_cfg_t
typedef void	ioport_ctrl_t
typedef struct st_ioport_api	ioport_api_t
typedef struct st_ioport_instance	ioport_instance_t
typedef struct st_mhu_callback_args	mhu_callback_args_t
typedef struct st_mhu_cfg	mhu_cfg_t
typedef void	mhu_ctrl_t
typedef struct st_mhu_api	mhu_api_t
typedef struct st_mhu_instance	mhu_instance_t
typedef struct st_mhu_ns_swint_get_callback_args	mhu_ns_swint_get_callback_args_t
typedef struct st_mhu_ns_swint_get_cfg	mhu_ns_swint_get_cfg_t
typedef void	mhu_ns_swint_get_ctrl_t
typedef struct st_mhu_ns_swint_get_api	mhu_ns_swint_get_api_t
typedef struct st_mhu_ns_swint_get_instance	mhu_ns_swint_get_instance_t
typedef struct st_mhu_ns_swint_set_callback_args	mhu_ns_swint_set_callback_args_t
typedef struct st_mhu_ns_swint_set_cfg	mhu_ns_swint_set_cfg_t
typedef void	mhu_ns_swint_set_ctrl_t
typedef struct st_mhu_ns_swint_set_api	mhu_ns_swint_set_api_t
typedef struct st_mhu_ns_swint_set_instance	mhu_ns_swint_set_instance_t
typedef struct st_pdm_callback_args	pdm_callback_args_t
typedef struct st_pdm_sound_detection_setting	pdm_sound_detection_setting_t
typedef void	pdm_ctrl_t
typedef struct st_pdm_status	pdm_status_t
typedef struct st_pdm_cfg	pdm_cfg_t
typedef struct st_pdm_api	pdm_api_t
typedef struct st_pdm_instance	pdm_instance_t
typedef struct st_poeg_status	poeg_status_t
typedef struct st_poeg_callback_args	poeg_callback_args_t
typedef void	poeg_ctrl_t
typedef struct st_poeg_cfg	poeg_cfg_t
typedef struct st_poeg_api	poeg_api_t
typedef struct st_poeg_instance	poeg_instance_t
typedef struct st_rtc_callback_args	rtc_callback_args_t
typedef struct st_rtc_error_adjustment_cfg	rtc_error_adjustment_cfg_t
typedef struct tm	rtc_time_t
typedef struct st_rtc_alarm_time	rtc_alarm_time_t
typedef struct st_rtc_time_capture	rtc_time_capture_t
typedef struct st_rtc_info	rtc_info_t
typedef struct st_rtc_cfg	rtc_cfg_t
typedef void	rtc_ctrl_t
typedef struct st_rtc_api	rtc_api_t
typedef struct st_rtc_instance	rtc_instance_t
typedef struct st_spi_callback_args	spi_callback_args_t
typedef struct st_spi_write_read_guard_args	spi_write_read_guard_args_t
typedef struct st_spi_cfg	spi_cfg_t
typedef void	spi_ctrl_t
typedef struct st_spi_api	spi_api_t
typedef struct st_spi_instance	spi_instance_t
typedef struct st_spi_flash_erase_command	spi_flash_erase_command_t
typedef struct st_spi_flash_direct_transfer	spi_flash_direct_transfer_t
typedef struct st_spi_flash_cfg	spi_flash_cfg_t
typedef void	spi_flash_ctrl_t
typedef struct st_spi_flash_status	spi_flash_status_t
typedef struct st_spi_flash_api	spi_flash_api_t
typedef struct st_spi_flash_instance	spi_flash_instance_t
typedef struct st_timer_callback_args	timer_callback_args_t
typedef void	timer_ctrl_t
typedef struct st_timer_info	timer_info_t
typedef struct st_timer_status	timer_status_t
typedef struct st_timer_cfg	timer_cfg_t
typedef struct st_timer_api	timer_api_t
typedef struct st_timer_instance	timer_instance_t
typedef void	transfer_ctrl_t
typedef struct st_transfer_callback_args_t	transfer_callback_args_t
typedef struct st_transfer_properties	transfer_properties_t
typedef struct st_transfer_info	transfer_info_t
typedef struct st_transfer_cfg	transfer_cfg_t
typedef struct st_transfer_api	transfer_api_t
typedef struct st_transfer_instance	transfer_instance_t
typedef struct st_uart_info	uart_info_t
typedef struct st_uart_callback_arg	uart_callback_args_t
typedef struct st_uart_cfg	uart_cfg_t
typedef void	uart_ctrl_t
typedef struct st_uart_api	uart_api_t
typedef struct st_uart_instance	uart_instance_t
typedef struct st_wdt_callback_args	wdt_callback_args_t
typedef struct st_wdt_timeout_values	wdt_timeout_values_t
typedef void	wdt_ctrl_t
typedef struct st_wdt_cfg	wdt_cfg_t
typedef struct st_wdt_api	wdt_api_t
typedef struct st_wdt_instance	wdt_instance_t
typedef struct st_rm_comms_write_read_params	rm_comms_write_read_params_t
typedef struct st_rm_comms_callback_args	rm_comms_callback_args_t
typedef struct st_rm_comms_cfg	rm_comms_cfg_t
typedef void	rm_comms_ctrl_t
typedef struct st_rm_comms_api	rm_comms_api_t
typedef struct st_rm_comms_instance	rm_comms_instance_t
typedef union st_fsp_pack_version	fsp_pack_version_t
typedef struct st_adc_c_extended_cfg	adc_c_extended_cfg_t
typedef struct st_adc_c_channel_cfg	adc_c_channel_cfg_t
typedef struct st_adc_c_instance_ctrl	adc_c_instance_ctrl_t
typedef struct st_adc_e_extended_cfg	adc_e_extended_cfg_t
typedef struct st_adc_e_window_cfg	adc_e_window_cfg_t
typedef struct st_adc_e_channel_cfg	adc_e_channel_cfg_t
typedef struct st_adc_e_instance_ctrl	adc_e_instance_ctrl_t
typedef struct st_canfd_instance_ctrl	canfd_instance_ctrl_t
typedef struct st_canfd_afl_entry	canfd_afl_entry_t
typedef struct st_canfd_global_cfg	canfd_global_cfg_t
typedef struct st_canfd_extended_cfg	canfd_extended_cfg_t
typedef struct st_cmtw_instance_ctrl	cmtw_instance_ctrl_t
typedef struct st_cmtw_extended_cfg	cmtw_extended_cfg_t
typedef struct st_crc_extended_cfg	crc_extended_cfg_t
typedef struct st_crc_instance_ctrl	crc_instance_ctrl_t
typedef struct st_dmac_b_register_set_setting_t	dmac_b_register_set_setting_t
typedef struct st_dmac_b_link_cfg	dmac_b_link_cfg_t
typedef struct st_dmac_b_instance_ctrl	dmac_b_instance_ctrl_t
typedef struct st_dmac_b_extended_cfg	dmac_b_extended_cfg_t
typedef struct st_dmac_b_extended_info	dmac_b_extended_info_t
typedef struct st_elc_instance_ctrl	elc_instance_ctrl_t
typedef struct s_gpt_output_pin	gpt_output_pin_t
typedef struct s_gpt_gtior_setting	gpt_gtior_setting_t
typedef struct st_gpt_instance_ctrl	gpt_instance_ctrl_t
typedef struct st_gpt_extended_pwm_cfg	gpt_extended_pwm_cfg_t
typedef struct st_gpt_extended_cfg	gpt_extended_cfg_t
typedef struct st_gtm_instance_ctrl	gtm_instance_ctrl_t
typedef struct st_gtm_extended_cfg	gtm_extended_cfg_t
typedef struct s_i3c_b_clock_stalling	i3c_b_clock_stalling_t
typedef struct s_i3c_b_bitrate_settings	i3c_b_bitrate_settings_t
typedef struct s_i3c_b_ibi_control	i3c_b_ibi_control_t
typedef struct s_i3c_b_slave_command_response_info	i3c_b_slave_command_response_info_t
typedef struct s_i3c_b_read_buffer_descriptor	i3c_b_read_buffer_descriptor_t
typedef struct s_i3c_b_write_buffer_descriptor	i3c_b_write_buffer_descriptor_t
typedef struct st_i3c_b_instance_ctrl	i3c_b_instance_ctrl_t
typedef struct s_i3c_b_extended_cfg	i3c_b_extended_cfg_t
typedef struct st_intc_irq_instance_ctrl	intc_irq_instance_ctrl_t
typedef struct st_intc_nmi_instance_ctrl	intc_nmi_instance_ctrl_t
typedef uint8_t	intc_tint_gpioint_t
typedef struct st_intc_tint_instance_ctrl	intc_tint_instance_ctrl_t
typedef struct st_intc_tint_extended_cfg	intc_tint_extended_cfg_t
typedef struct st_ioport_instance_ctrl	ioport_instance_ctrl_t
typedef struct st_ioport_event_single	ioport_event_single_t
typedef struct st_ioport_event_group_output	ioport_event_group_output_t
typedef struct st_ioport_event_group_input	ioport_event_group_input_t
typedef struct st_ioport_extend_cfg	ioport_extend_cfg_t
typedef struct st_mhu_b_ns_instance_ctrl	mhu_b_ns_instance_ctrl_t
typedef struct st_mhu_b_ns_extended_cfg	mhu_b_ns_extended_cfg_t
typedef struct st_mhu_b_ns_swint_get_instance_ctrl	mhu_b_ns_swint_get_instance_ctrl_t
typedef struct st_mhu_b_ns_swint_get_extended_cfg	mhu_b_ns_swint_get_extended_cfg_t
typedef struct st_mhu_b_ns_swint_set_instance_ctrl	mhu_b_ns_swint_set_instance_ctrl_t
typedef struct st_mhu_b_ns_swint_set_extended_cfg	mhu_b_ns_swint_set_extended_cfg_t
typedef struct st_mhu_b_s_instance_ctrl	mhu_b_s_instance_ctrl_t
typedef struct st_mhu_b_s_extended_cfg	mhu_b_s_extended_cfg_t
typedef struct st_mhu_ns_instance_ctrl	mhu_ns_instance_ctrl_t
typedef struct st_mhu_ns_extended_cfg	mhu_ns_extended_cfg_t
typedef struct st_mhu_ns_swint_get_instance_ctrl	mhu_ns_swint_get_instance_ctrl_t
typedef struct st_mhu_ns_swint_get_extended_cfg	mhu_ns_swint_get_extended_cfg_t
typedef struct st_mhu_ns_swint_set_instance_ctrl	mhu_ns_swint_set_instance_ctrl_t
typedef struct st_mhu_ns_swint_set_extended_cfg	mhu_ns_swint_set_extended_cfg_t
typedef struct st_mhu_s_instance_ctrl	mhu_s_instance_ctrl_t
typedef struct st_mhu_s_extended_cfg	mhu_s_extended_cfg_t
typedef struct st_mtu3_output_pin	mtu3_output_pin_t
typedef struct st_mtu3_instance_ctrl	mtu3_instance_ctrl_t
typedef struct st_mtu3_extended_pwm_cfg	mtu3_extended_pwm_cfg_t
typedef struct st_mtu3_extended_cfg	mtu3_extended_cfg_t
typedef struct st_pdm_instance_ctrl	pdm_instance_ctrl_t
typedef struct st_pdm_extended_cfg	pdm_extended_cfg_t
typedef struct st_poeg_instance_ctrl	poeg_instance_ctrl_t
typedef struct st_poeg_extended_cfg	poeg_extended_cfg_t
typedef struct iic_master_clock_settings	iic_master_clock_settings_t
typedef struct st_iic_master_instance_ctrl	iic_master_instance_ctrl_t
typedef struct st_riic_master_extended_cfg	riic_master_extended_cfg_t
typedef struct iic_slave_clock_settings	iic_slave_clock_settings_t
typedef struct st_iic_slave_instance_ctrl	iic_slave_instance_ctrl_t
typedef struct st_riic_slave_extended_cfg	riic_slave_extended_cfg_t
typedef struct st_rspi_rspck_div_setting	rspi_rspck_div_setting_t
typedef struct st_rspi_extended_cfg	rspi_extended_cfg_t
typedef struct st_rspi_instance_ctrl	rspi_instance_ctrl_t
typedef struct st_rtc_extended_cfg	rtc_extended_cfg_t
typedef struct st_rtc_ctrl	rtc_instance_ctrl_t
typedef struct st_sci_b_i2c_clock_settings	sci_b_i2c_clock_settings_t
typedef struct st_sci_b_i2c_instance_ctrl	sci_b_i2c_instance_ctrl_t
typedef struct st_sci_b_i2c_extended_cfg	sci_b_i2c_extended_cfg_t
typedef struct st_sci_b_spi_div_setting	sci_b_spi_div_setting_t
typedef struct st_sci_b_spi_extended_cfg	sci_b_spi_extended_cfg_t
typedef struct st_sci_b_spi_instance_ctrl	sci_b_spi_instance_ctrl_t
typedef struct st_sci_b_uart_instance_ctrl	sci_b_uart_instance_ctrl_t
typedef struct st_sci_b_baud_setting_t	sci_b_baud_setting_t
typedef struct st_sci_b_uart_rs485_setting	sci_b_uart_rs485_setting_t
typedef struct st_sci_b_uart_sci_b_uart_half_data_setting	sci_b_uart_half_data_setting_t
typedef struct st_sci_b_uart_extended_cfg	sci_b_uart_extended_cfg_t
typedef struct st_sci_uart_instance_ctrl	sci_uart_instance_ctrl_t
typedef struct st_baud_setting	baud_setting_t
typedef struct st_sci_uart_rs485_setting	sci_uart_rs485_setting_t
typedef struct st_sci_uart_extended_cfg	sci_uart_extended_cfg_t
typedef struct st_scif_uart_instance_ctrl	scif_uart_instance_ctrl_t
typedef struct st_scif_baud_setting	scif_baud_setting_t
typedef struct st_scif_uart_rs485_setting	scif_uart_rs485_setting_t
typedef struct st_scif_uart_extended_cfg	scif_uart_extended_cfg_t
typedef struct st_rspck_div_setting	rspck_div_setting_t
typedef struct st_spi_b_extended_cfg	spi_b_extended_cfg_t
typedef struct st_spi_b_instance_ctrl	spi_b_instance_ctrl_t
typedef struct st_tsu_b_extended_cfg	tsu_b_extended_cfg_t
typedef struct st_tsu_b_instance_ctrl	tsu_b_instance_ctrl_t
typedef struct st_wdt_instance_ctrl	wdt_instance_ctrl_t
typedef struct st_wdt_extended_cfg	wdt_extended_cfg_t
typedef struct st_qspi_timing_setting	xspi_qspi_timing_setting_t
typedef struct st_xspi_qspi_instance_ctrl	xspi_qspi_instance_ctrl_t
typedef struct st_xspi_qspi_extended_cfg	xspi_qspi_extended_cfg_t
typedef struct st_rm_comms_i2c_bus_extended_cfg	rm_comms_i2c_bus_extended_cfg_t
typedef struct st_rm_comms_i2c_instance_ctrl	rm_comms_i2c_instance_ctrl_t

Enumerations
enum	fsp_err_t
enum	adc_mode_t
enum	adc_resolution_t
enum	adc_alignment_t
enum	adc_trigger_t
enum	adc_event_t
enum	adc_channel_t
enum	adc_group_id_t
enum	adc_group_mask_t
enum	adc_state_t
enum	can_event_t
enum	can_operation_mode_t
enum	can_test_mode_t
enum	can_id_mode_t
enum	can_frame_type_t
enum	crc_polynomial_t
enum	crc_bit_order_t
enum	crc_snoop_direction_t
enum	elc_peripheral_t
enum	elc_software_event_t
enum	external_irq_trigger_t
enum	external_irq_clock_source_div_t
enum	i2c_master_rate_t
enum	i2c_master_addr_mode_t
enum	i2c_master_event_t
enum	i2c_slave_rate_t
enum	i2c_slave_addr_mode_t
enum	i2c_slave_event_t
enum	i3c_common_command_code_t
enum	i3c_event_t
enum	i3c_device_type_t
enum	i3c_device_protocol_t
enum	i3c_address_assignment_mode_t
enum	i3c_ibi_type_t
enum	mhu_send_type_t
enum	pdm_pcm_width_t
enum	pdm_input_data_edge_t
enum	pdm_event_t
enum	pdm_error_t
enum	pdm_state_t
enum	poeg_state_t
enum	poeg_trigger_t
enum	poeg_gtetrg_polarity_t
enum	poeg_gtetrg_noise_filter_t
enum	rtc_event_t
enum	rtc_alarm_channel_t
enum	rtc_clock_source_t
enum	rtc_status_t
enum	rtc_error_adjustment_t
enum	rtc_error_adjustment_mode_t
enum	rtc_error_adjustment_period_t
enum	rtc_periodic_irq_select_t
enum	rtc_time_capture_source_t
enum	rtc_time_capture_mode_t
enum	rtc_time_capture_noise_filter_t
enum	spi_bit_width_t
enum	spi_mode_t
enum	spi_clk_phase_t
enum	spi_clk_polarity_t
enum	spi_mode_fault_t
enum	spi_bit_order_t
enum	spi_event_t
enum	spi_flash_read_mode_t
enum	spi_flash_protocol_t
enum	spi_flash_address_bytes_t
enum	spi_flash_data_lines_t
enum	spi_flash_dummy_clocks_t
enum	spi_flash_direct_transfer_dir_t
enum	timer_event_t
enum	timer_variant_t
enum	timer_compare_match_t
enum	timer_state_t
enum	timer_mode_t
enum	timer_direction_t
enum	timer_source_div_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	transfer_repeat_area_t
enum	transfer_chain_mode_t
enum	transfer_irq_t
enum	transfer_start_mode_t
enum	uart_event_t
enum	uart_data_bits_t
enum	uart_parity_t
enum	uart_stop_bits_t
enum	uart_dir_t
enum	wdt_timeout_t
enum	wdt_clock_division_t
enum	wdt_window_start_t
enum	wdt_window_end_t
enum	wdt_reset_control_t
enum	wdt_stop_control_t
enum	wdt_status_t
enum	rm_comms_event_t
enum	fsp_ip_t
enum	adc_c_mask_t
enum	adc_c_trigger_mode_t
enum	adc_c_active_trigger_t
enum	adc_c_trigger_edge_t
enum	adc_c_input_mode_t
enum	adc_c_operating_mode_t
enum	adc_c_buffer_mode_t
enum	adc_c_filter_stage_setting_t
enum	adc_c_interrupt_channel_setting_t
enum	adc_e_mask_t
enum	adc_e_add_t
enum	adc_e_clear_t
enum	adc_e_grpa_t
enum	adc_e_active_trigger_t
enum	adc_e_double_trigger_t
enum	adc_e_compare_cfg_t
enum	adc_e_window_b_channel_t
enum	adc_e_window_b_mode_t
enum	adc_e_elc_t
enum	canfd_status_t
enum	canfd_error_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	canfd_rx_buffer_t
enum	canfd_rx_mb_t
enum	canfd_rx_fifo_t
enum	canfd_minimum_dlc_t
enum	canfd_frame_options_t
enum	canfd_txmb_merge_mode_t
enum	cmtw_source_edge_t
enum	cmtw_output_pin_t
enum	cmtw_clear_source_t
enum	cmtw_io_pin_t
enum	cmtw_output_control_t
enum	cmtw_input_control_t
enum	dmac_b_transfer_size_t
enum	dmac_b_ack_mode_t
enum	dmac_b_external_detection_t
enum	dmac_b_internal_detection_t
enum	dmac_b_request_direction_t
enum	dmac_b_continuous_setting_t
enum	dmac_b_channel_scheduling_t
enum	dmac_b_mode_select_t
enum	dmac_b_link_valid_t
enum	dmac_b_link_end_t
enum	dmac_b_link_write_back_t
enum	dmac_b_link_interrupt_mask_t
enum	gpt_io_pin_t
enum	gpt_buffer_force_push
enum	gpt_pin_level_t
enum	gpt_source_t
enum	gpt_capture_filter_t
enum	gpt_adc_trigger_t
enum	gpt_poeg_link_t
enum	gpt_output_disable_t
enum	gpt_gtioc_disable_t
enum	gpt_adc_compare_match_t
enum	gpt_interrupt_skip_source_t
enum	gpt_interrupt_skip_count_t
enum	gpt_interrupt_skip_adc_t
enum	gpt_interrupt_skip_select_t
enum	gpt_pwm_output_delay_setting_t
enum	gpt_pwm_output_delay_edge_t
enum	gtm_giws_type_t
enum	gtm_timer_mode_t
enum	i3c_b_bitrate_mode_t
enum	i3c_b_activity_state_t
enum	i3c_b_data_rate_setting_t
enum	i3c_b_clock_data_turnaround_t
enum	intc_tint_trigger_t
enum	ioport_peripheral_t
enum	ioport_cfg_options_t
enum	ioport_event_pin_selection_t
enum	ioport_event_output_operation_t
enum	ioport_event_control_t
enum	ioport_event_direction_t
enum	ioport_event_detection_t
enum	ioport_event_initial_buffer_value_t
enum	ioport_noise_filter_irq_port_offset_t
enum	ioport_noise_filter_dreq_port_offset_t
enum	mtu3_io_pin_level_t
enum	mtu3_clock_edge_t
enum	mtu3_clock_div_t
enum	mtu3_tcnt_clear_t
enum	mtu3_io_pin_t
enum	mtu3_pin_level_t
enum	mtu3_noise_filter_t
enum	mtu3_noise_filter_mtclk_t
enum	mtu3_noise_filter_clock_t
enum	mtu3_noise_filter_external_clock_t
enum	mtu3_interrupt_skip_mode_t
enum	mtu3_interrupt_skip_count_t
enum	mtu3_adc_compare_match_t
enum	mtu3_adc_activation_tgra_compare_match_t
enum	mtu3_buffer_mode_t
enum	mtu3_phase_counting_mode_t
enum	mtu3_bit_mode_t
enum	mtu3_external_clock_t
enum	pdm_clk_div_t
enum	pdm_moving_average_mode_t
enum	pdm_low_pass_filter_shift_t
enum	pdm_compensation_filter_shift_t
enum	pdm_high_pass_filter_shift_t
enum	pdm_sinc_filter_mode_t
enum	pdm_interrupt_threshold_t
enum	pdm_short_circuit_enable_t
enum	pdm_overvoltage_lower_limit_enable_t
enum	pdm_overvoltage_upper_limit_enable_t
enum	pdm_buffer_overwrite_detection_enable_t
enum	iic_master_timeout_mode_t
enum	iic_master_timeout_scl_low_t
enum	rspi_ssl_polarity_t
enum	rspi_mosi_idle_value_fixing_t
enum	rspi_ssl_level_keep_t
enum	rspi_delay_count_t
enum	rspi_tx_trigger_level_t
enum	rspi_rx_trigger_level_t
enum	rtc_clock_bypass_mode_t
enum	sci_b_i2c_clock_source_t
enum	sci_b_spi_clock_source_t
enum	sci_b_spi_rx_sampling_delay_t
enum	sci_b_clk_src_t
enum	sci_b_uart_flow_control_t
enum	sci_b_uart_rx_fifo_trigger_t
enum	sci_b_uart_start_bit_detect_t
enum	sci_b_uart_noise_cancellation_t
enum	sci_b_uart_rs485_enable_t
enum	sci_b_uart_rs485_de_polarity_t
enum	sci_b_uart_half_data_enable_t
enum	sci_clk_src_t
enum	sci_uart_flow_control_t
enum	sci_uart_rx_fifo_trigger_t
enum	sci_uart_start_bit_t
enum	sci_uart_noise_cancellation_t
enum	sci_uart_rs485_enable_t
enum	sci_uart_rs485_de_polarity_t
enum	scif_clk_src_t
enum	scif_uart_mode_t
enum	scif_uart_flow_control_t
enum	scif_uart_noise_cancellation_t
enum	scif_uart_rs485_enable_t
enum	scif_uart_rs485_de_polarity_t
enum	scif_uart_rx_fifo_trigger_t
enum	scif_uart_rts_trigger_t
enum	spi_b_ssl_mode_t
enum	spi_b_communication_t
enum	spi_b_ssl_polarity_t
enum	spi_b_ssl_select_t
enum	spi_b_mosi_idle_value_fixing_t
enum	spi_b_parity_t
enum	spi_b_byte_swap_t
enum	spi_b_delay_count_t
enum	spi_b_clock_source_t
enum	spi_b_ssl_level_keep_t
enum	tsu_b_average_t
enum	tsu_b_compare_cfg_t
enum	xspi_qspi_chip_select_t
enum	xspi_qspi_memory_size_t
enum	xspi_qspi_command_interval_clocks_t
enum	xspi_qspi_cs_pullup_clocks_t
enum	xspi_qspi_cs_pulldown_clocks_t
enum	xspi_qspi_prefetch_function_t
enum	bsp_warm_start_event_t
enum	bsp_delay_units_t
enum	bsp_grp_irq_t
enum	bsp_io_level_t
enum	bsp_io_direction_t
enum	bsp_io_port_t
enum	bsp_io_port_pin_t
enum	bsp_sd_channel_t
enum	bsp_ethernet_channel_t
enum	bsp_sd_voltage_t
enum	bsp_qspi_voltage_t
enum	bsp_xspi_voltage_t
enum	bsp_ethernet_voltage_t
enum	bsp_i3c_voltage_t
enum	bsp_ethernet_mode_t
enum	bsp_i3c_mode_t
enum	bsp_bypass_oscillator_t
enum	bsp_bypass_mode_t
enum	bsp_bypass_freq_range_t
enum	intsel_cause_t
enum	dmac_b_external_detection_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	bsp_io_port_t
enum	bsp_io_port_pin_t
enum	bsp_system_reset_signal_t
enum	dmac_b_external_detection_t
enum	fsp_acc_control_ip_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	elc_event_t
enum	bsp_io_port_t
enum	bsp_io_port_pin_t
enum	canfd_error_t
enum	canfd_rx_buffer_t
enum	canfd_rx_fifo_t
enum	canfd_rx_mb_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	fsp_acc_control_ip_t
enum	fsp_ip_t
enum	fsp_mst_acc_control_ip_t
enum	bsp_system_reset_signal_t
enum	elc_peripheral_t
enum	elc_software_event_t
enum	gpt_source_t
enum	ioport_cfg_options_t
enum	spi_b_clock_source_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t
enum	bsp_io_port_t
enum	bsp_io_port_pin_t
enum	bsp_system_reset_signal_t
enum	canfd_tx_buffer_t
enum	canfd_tx_mb_t
enum	dmac_b_external_detection_t
enum	fsp_acc_control_ip_t
enum	fsp_mst_acc_control_ip_t
enum	ioport_peripheral_t
enum	transfer_event_t
enum	transfer_mode_t
enum	transfer_size_t
enum	transfer_addr_mode_t

Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)
fsp_err_t	R_ADC_C_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_ADC_C_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg)
fsp_err_t	R_ADC_C_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_ADC_C_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_C_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_id)
fsp_err_t	R_ADC_C_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_C_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_ADC_C_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_ADC_C_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_ADC_C_SampleStateCountSet (adc_ctrl_t *p_ctrl, uint16_t num_states)
fsp_err_t	R_ADC_C_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_C_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_ADC_C_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_ADC_C_CallbackSet (adc_ctrl_t *const p_api_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_ADC_E_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_ADC_E_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg)
fsp_err_t	R_ADC_E_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_ADC_E_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_E_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_id)
fsp_err_t	R_ADC_E_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_E_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_ADC_E_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_ADC_E_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_ADC_E_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_ADC_E_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_ADC_E_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_ADC_E_CallbackSet (adc_ctrl_t *const p_api_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_CANFD_Open (can_ctrl_t *const p_api_ctrl, can_cfg_t const *const p_cfg)
fsp_err_t	R_CANFD_Close (can_ctrl_t *const p_api_ctrl)
fsp_err_t	R_CANFD_Write (can_ctrl_t *const p_api_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_Read (can_ctrl_t *const p_api_ctrl, uint32_t const buffer, can_frame_t *const p_frame)
fsp_err_t	R_CANFD_ModeTransition (can_ctrl_t *const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode)
fsp_err_t	R_CANFD_InfoGet (can_ctrl_t *const p_api_ctrl, can_info_t *const p_info)
fsp_err_t	R_CANFD_CallbackSet (can_ctrl_t *const p_api_ctrl, void(*p_callback)(can_callback_args_t *), void *const p_context, can_callback_args_t *const p_callback_memory)
fsp_err_t	R_CMTW_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_CMTW_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_CMTW_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_CMTW_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_CMTW_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_CMTW_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_CMTW_OutputEnable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin)
fsp_err_t	R_CMTW_OutputDisable (timer_ctrl_t *const p_ctrl, cmtw_io_pin_t pin)
fsp_err_t	R_CMTW_CallbackSet (timer_ctrl_t *const p_api_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_CRC_Open (crc_ctrl_t *const p_ctrl, crc_cfg_t const *const p_cfg)
fsp_err_t	R_CRC_Close (crc_ctrl_t *const p_ctrl)
fsp_err_t	R_CRC_Calculate (crc_ctrl_t *const p_ctrl, crc_input_t *const p_crc_input, uint32_t *calculatedValue)
fsp_err_t	R_CRC_CalculatedValueGet (crc_ctrl_t *const p_ctrl, uint32_t *calculatedValue)
fsp_err_t	R_CRC_SnoopEnable (crc_ctrl_t *const p_ctrl, uint32_t crc_seed)
fsp_err_t	R_CRC_SnoopDisable (crc_ctrl_t *const p_ctrl)
fsp_err_t	R_DMAC_B_Open (transfer_ctrl_t *const p_api_ctrl, transfer_cfg_t const *const p_cfg)
fsp_err_t	R_DMAC_B_Reconfigure (transfer_ctrl_t *const p_api_ctrl, transfer_info_t *p_info)
fsp_err_t	R_DMAC_B_Reset (transfer_ctrl_t *const p_api_ctrl, void const *volatile p_src, void *volatile p_dest, uint16_t const num_transfers)
fsp_err_t	R_DMAC_B_SoftwareStart (transfer_ctrl_t *const p_api_ctrl, transfer_start_mode_t mode)
fsp_err_t	R_DMAC_B_SoftwareStop (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Enable (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Disable (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_InfoGet (transfer_ctrl_t *const p_api_ctrl, transfer_properties_t *const p_info)
fsp_err_t	R_DMAC_B_Close (transfer_ctrl_t *const p_api_ctrl)
fsp_err_t	R_DMAC_B_Reload (transfer_ctrl_t *const p_api_ctrl, void const *p_src, void *p_dest, uint32_t const num_transfers)
fsp_err_t	R_DMAC_B_CallbackSet (transfer_ctrl_t *const p_api_ctrl, void(*p_callback)(dmac_b_callback_args_t *), void *const p_context, dmac_b_callback_args_t *const p_callback_memory)
fsp_err_t	R_DMAC_B_LinkDescriptorSet (transfer_ctrl_t *const p_api_ctrl, dmac_b_link_cfg_t *p_descriptor)
fsp_err_t	R_ELC_Open (elc_ctrl_t *const p_ctrl, elc_cfg_t const *const p_cfg)
fsp_err_t	R_ELC_Close (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_ELC_SoftwareEventGenerate (elc_ctrl_t *const p_ctrl, elc_software_event_t event_number)
fsp_err_t	R_ELC_LinkSet (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral, elc_event_t signal)
fsp_err_t	R_ELC_LinkBreak (elc_ctrl_t *const p_ctrl, elc_peripheral_t peripheral)
fsp_err_t	R_ELC_Enable (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_ELC_Disable (elc_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_GPT_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_GPT_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_GPT_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_GPT_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_GPT_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_GPT_OutputEnable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)
fsp_err_t	R_GPT_OutputDisable (timer_ctrl_t *const p_ctrl, gpt_io_pin_t pin)
fsp_err_t	R_GPT_AdcTriggerSet (timer_ctrl_t *const p_ctrl, gpt_adc_compare_match_t which_compare_match, uint32_t compare_match_value)
fsp_err_t	R_GPT_PwmOutputDelaySet (timer_ctrl_t *const p_ctrl, gpt_pwm_output_delay_edge_t edge, gpt_pwm_output_delay_setting_t delay_setting, uint32_t const pin)
fsp_err_t	R_GPT_CallbackSet (timer_ctrl_t *const p_api_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_GPT_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GPT_PwmOutputDelayInitialize (void)
fsp_err_t	R_GPT_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_GTM_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_GTM_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_GTM_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_GTM_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_GTM_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_GTM_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_GTM_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_I3C_B_Open (i3c_ctrl_t *const p_api_ctrl, i3c_cfg_t const *const p_cfg)
fsp_err_t	R_I3C_B_Enable (i3c_ctrl_t *const p_api_ctrl)
fsp_err_t	R_I3C_B_DeviceCfgSet (i3c_ctrl_t *const p_api_ctrl, i3c_device_cfg_t const *const p_device_cfg)
fsp_err_t	R_I3C_B_MasterDeviceTableSet (i3c_ctrl_t *const p_api_ctrl, uint32_t device_index, i3c_device_table_cfg_t const *const p_device_table_cfg)
fsp_err_t	R_I3C_B_SlaveStatusSet (i3c_ctrl_t *const p_api_ctrl, i3c_device_status_t status)
fsp_err_t	R_I3C_B_DeviceSelect (i3c_ctrl_t *const p_api_ctrl, uint32_t device_index, uint32_t bitrate_mode)
fsp_err_t	R_I3C_B_DynamicAddressAssignmentStart (i3c_ctrl_t *const p_api_ctrl, i3c_address_assignment_mode_t address_assignment_mode, uint32_t starting_device_index, uint32_t device_count)
fsp_err_t	R_I3C_B_CommandSend (i3c_ctrl_t *const p_api_ctrl, i3c_command_descriptor_t const *const p_command_descriptor)
fsp_err_t	R_I3C_B_Write (i3c_ctrl_t *const p_api_ctrl, uint8_t const *const p_data, uint32_t length, bool restart)
fsp_err_t	R_I3C_B_Read (i3c_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t length, bool restart)
fsp_err_t	R_I3C_B_IbiWrite (i3c_ctrl_t *const p_api_ctrl, i3c_ibi_type_t ibi_type, uint8_t const *const p_data, uint32_t length)
fsp_err_t	R_I3C_B_IbiRead (i3c_ctrl_t *const p_api_ctrl, uint8_t *const p_data, uint32_t length)
fsp_err_t	R_I3C_B_Close (i3c_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_IRQ_ExternalIrqOpen (external_irq_ctrl_t *const p_api_ctrl, external_irq_cfg_t const *const p_cfg)
fsp_err_t	R_INTC_IRQ_ExternalIrqEnable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_IRQ_ExternalIrqDisable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_IRQ_ExternalIrqCallbackSet (external_irq_ctrl_t *const p_api_ctrl, void(*p_callback)(external_irq_callback_args_t *), void *const p_context, external_irq_callback_args_t *const p_callback_memory)
fsp_err_t	R_INTC_IRQ_ExternalIrqClose (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_NMI_ExternalIrqOpen (external_irq_ctrl_t *const p_api_ctrl, external_irq_cfg_t const *const p_cfg)
fsp_err_t	R_INTC_NMI_ExternalIrqEnable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_NMI_ExternalIrqDisable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_NMI_ExternalIrqCallbackSet (external_irq_ctrl_t *const p_api_ctrl, void(*p_callback)(external_irq_callback_args_t *), void *const p_context, external_irq_callback_args_t *const p_callback_memory)
fsp_err_t	R_INTC_NMI_ExternalIrqClose (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_TINT_ExternalIrqOpen (external_irq_ctrl_t *const p_api_ctrl, external_irq_cfg_t const *const p_cfg)
fsp_err_t	R_INTC_TINT_ExternalIrqEnable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_TINT_ExternalIrqDisable (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_INTC_TINT_ExternalIrqCallbackSet (external_irq_ctrl_t *const p_api_ctrl, void(*p_callback)(external_irq_callback_args_t *), void *const p_context, external_irq_callback_args_t *const p_callback_memory)
fsp_err_t	R_INTC_TINT_ExternalIrqClose (external_irq_ctrl_t *const p_api_ctrl)
fsp_err_t	R_IOPORT_Open (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg)
fsp_err_t	R_IOPORT_Close (ioport_ctrl_t *const p_ctrl)
fsp_err_t	R_IOPORT_PinsCfg (ioport_ctrl_t *const p_ctrl, const ioport_cfg_t *p_cfg)
fsp_err_t	R_IOPORT_PinCfg (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, uint32_t cfg)
fsp_err_t	R_IOPORT_PinEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_event)
fsp_err_t	R_IOPORT_PinEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t pin_value)
fsp_err_t	R_IOPORT_PinRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t *p_pin_value)
fsp_err_t	R_IOPORT_PinWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_pin_t pin, bsp_io_level_t level)
fsp_err_t	R_IOPORT_PortDirectionSet (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t direction_values, ioport_size_t mask)
fsp_err_t	R_IOPORT_PortEventInputRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *event_data)
fsp_err_t	R_IOPORT_PortEventOutputWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t event_data, ioport_size_t mask_value)
fsp_err_t	R_IOPORT_PortRead (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t *p_port_value)
fsp_err_t	R_IOPORT_PortWrite (ioport_ctrl_t *const p_ctrl, bsp_io_port_t port, ioport_size_t value, ioport_size_t mask)
fsp_err_t	R_MHU_B_NS_Open (mhu_ctrl_t *p_ctrl, mhu_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_B_NS_MsgSend (mhu_ctrl_t *const p_ctrl, uint32_t const msg)
fsp_err_t	R_MHU_B_NS_Close (mhu_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_B_NS_CallbackSet (mhu_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_callback_args_t *), void *const p_context, mhu_callback_args_t *const p_callback_memory)
void	R_MHU_B_NS_IsrSub (uint32_t irq)
fsp_err_t	R_MHU_B_NS_SWINT_GET_Open (mhu_ns_swint_get_ctrl_t *p_ctrl, mhu_ns_swint_get_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_B_NS_SWINT_GET_Close (mhu_ns_swint_get_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_B_NS_SWINT_GET_CallbackSet (mhu_ns_swint_get_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_ns_swint_get_callback_args_t *), void *const p_context, mhu_ns_swint_get_callback_args_t *const p_callback_memory)
void	R_MHU_B_NS_SWINT_GET_IsrSub (uint32_t irq)
fsp_err_t	R_MHU_B_NS_SWINT_SET_Open (mhu_ns_swint_set_ctrl_t *p_ctrl, mhu_ns_swint_set_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_B_NS_SWINT_SET_InterruptSet (mhu_ns_swint_set_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_B_NS_SWINT_SET_Close (mhu_ns_swint_set_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_B_S_Open (mhu_ctrl_t *p_ctrl, mhu_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_B_S_MsgSend (mhu_ctrl_t *const p_ctrl, uint32_t const msg)
fsp_err_t	R_MHU_B_S_Close (mhu_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_B_S_CallbackSet (mhu_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_callback_args_t *), void *const p_context, mhu_callback_args_t *const p_callback_memory)
void	R_MHU_B_S_IsrSub (uint32_t irq)
fsp_err_t	R_MHU_NS_Open (mhu_ctrl_t *p_ctrl, mhu_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_NS_MsgSend (mhu_ctrl_t *const p_ctrl, uint32_t const msg)
fsp_err_t	R_MHU_NS_Close (mhu_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_NS_CallbackSet (mhu_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_callback_args_t *), void *const p_context, mhu_callback_args_t *const p_callback_memory)
void	R_MHU_NS_IsrSub (uint32_t irq)
fsp_err_t	R_MHU_NS_SWINT_GET_Open (mhu_ns_swint_get_ctrl_t *p_ctrl, mhu_ns_swint_get_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_NS_SWINT_GET_Close (mhu_ns_swint_get_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_NS_SWINT_GET_CallbackSet (mhu_ns_swint_get_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_ns_swint_get_callback_args_t *), void *const p_context, mhu_ns_swint_get_callback_args_t *const p_callback_memory)
void	R_MHU_NS_SWINT_GET_IsrSub (uint32_t irq)
fsp_err_t	R_MHU_NS_SWINT_SET_Open (mhu_ns_swint_set_ctrl_t *p_ctrl, mhu_ns_swint_set_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_NS_SWINT_SET_InterruptSet (mhu_ns_swint_set_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_NS_SWINT_SET_Close (mhu_ns_swint_set_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_S_Open (mhu_ctrl_t *p_ctrl, mhu_cfg_t const *const p_cfg)
fsp_err_t	R_MHU_S_MsgSend (mhu_ctrl_t *const p_ctrl, uint32_t const msg)
fsp_err_t	R_MHU_S_Close (mhu_ctrl_t *const p_ctrl)
fsp_err_t	R_MHU_S_CallbackSet (mhu_ctrl_t *const p_api_ctrl, void(*p_callback)(mhu_callback_args_t *), void *const p_context, mhu_callback_args_t *const p_callback_memory)
void	R_MHU_S_IsrSub (uint32_t irq)
fsp_err_t	R_MTU3_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_MTU3_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_PeriodSet (timer_ctrl_t *const p_ctrl, uint32_t const period_counts)
fsp_err_t	R_MTU3_DutyCycleSet (timer_ctrl_t *const p_ctrl, uint32_t const duty_cycle_counts, uint32_t const pin)
fsp_err_t	R_MTU3_InfoGet (timer_ctrl_t *const p_ctrl, timer_info_t *const p_info)
fsp_err_t	R_MTU3_StatusGet (timer_ctrl_t *const p_ctrl, timer_status_t *const p_status)
fsp_err_t	R_MTU3_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_MTU3_OutputEnable (timer_ctrl_t *const p_ctrl, mtu3_output_pin_t pin_level)
fsp_err_t	R_MTU3_OutputDisable (timer_ctrl_t *const p_ctrl, mtu3_io_pin_t pin)
fsp_err_t	R_MTU3_Enable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Disable (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_AdcTriggerSet (timer_ctrl_t *const p_ctrl, mtu3_adc_compare_match_t which_compare_match, uint16_t compare_match_value)
fsp_err_t	R_MTU3_CallbackSet (timer_ctrl_t *const p_api_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_MTU3_Close (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_CompareMatchSet (timer_ctrl_t *const p_ctrl, uint32_t const compare_match_value, timer_compare_match_t const match_channel)
fsp_err_t	R_PDM_Open (pdm_ctrl_t *const p_ctrl, pdm_cfg_t const *const p_cfg)
fsp_err_t	R_PDM_Start (pdm_ctrl_t *const p_ctrl, void *const p_buffer, size_t const buffer_size, uint32_t const number_of_data_to_callback)
fsp_err_t	R_PDM_Stop (pdm_ctrl_t *const p_ctrl)
fsp_err_t	R_PDM_SoundDetectionEnable (pdm_ctrl_t *const p_ctrl, pdm_sound_detection_setting_t sound_detection_setting)
fsp_err_t	R_PDM_SoundDetectionDisable (pdm_ctrl_t *const p_ctrl)
fsp_err_t	R_PDM_Read (pdm_ctrl_t *const p_ctrl, void *const p_dest, uint32_t const bytes)
fsp_err_t	R_PDM_StatusGet (pdm_ctrl_t *const p_ctrl, pdm_status_t *const p_status)
fsp_err_t	R_PDM_Close (pdm_ctrl_t *const p_ctrl)
fsp_err_t	R_PDM_CallbackSet (pdm_ctrl_t *const p_ctrl, void(*p_callback)(pdm_callback_args_t *), void *const p_context, pdm_callback_args_t *const p_callback_memory)
fsp_err_t	R_POEG_Open (poeg_ctrl_t *const p_ctrl, poeg_cfg_t const *const p_cfg)
fsp_err_t	R_POEG_StatusGet (poeg_ctrl_t *const p_ctrl, poeg_status_t *const p_status)
fsp_err_t	R_POEG_CallbackSet (poeg_ctrl_t *const p_ctrl, void(*p_callback)(poeg_callback_args_t *), void *const p_context, poeg_callback_args_t *const p_callback_memory)
fsp_err_t	R_POEG_OutputDisable (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_POEG_Reset (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_POEG_Close (poeg_ctrl_t *const p_ctrl)
fsp_err_t	R_RIIC_MASTER_Open (i2c_master_ctrl_t *const p_api_ctrl, i2c_master_cfg_t const *const p_cfg)
fsp_err_t	R_RIIC_MASTER_Read (i2c_master_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart)
fsp_err_t	R_RIIC_MASTER_Write (i2c_master_ctrl_t *const p_api_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart)
fsp_err_t	R_RIIC_MASTER_Abort (i2c_master_ctrl_t *const p_api_ctrl)
fsp_err_t	R_RIIC_MASTER_SlaveAddressSet (i2c_master_ctrl_t *const p_api_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode)
fsp_err_t	R_RIIC_MASTER_Close (i2c_master_ctrl_t *const p_api_ctrl)
fsp_err_t	R_RIIC_MASTER_CallbackSet (i2c_master_ctrl_t *const p_api_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory)
fsp_err_t	R_RIIC_MASTER_StatusGet (i2c_master_ctrl_t *const p_api_ctrl, i2c_master_status_t *p_status)
fsp_err_t	R_RIIC_SLAVE_Open (i2c_slave_ctrl_t *const p_api_ctrl, i2c_slave_cfg_t const *const p_cfg)
fsp_err_t	R_RIIC_SLAVE_Read (i2c_slave_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_RIIC_SLAVE_Write (i2c_slave_ctrl_t *const p_api_ctrl, uint8_t *const p_src, uint32_t const bytes)
fsp_err_t	R_RIIC_SLAVE_Close (i2c_slave_ctrl_t *const p_api_ctrl)
fsp_err_t	R_RIIC_SLAVE_CallbackSet (i2c_slave_ctrl_t *const p_api_ctrl, void(*p_callback)(i2c_slave_callback_args_t *), void *const p_context, i2c_slave_callback_args_t *const p_callback_memory)
fsp_err_t	R_RSPI_Open (spi_ctrl_t *p_api_ctrl, spi_cfg_t const *const p_cfg)
fsp_err_t	R_RSPI_Read (spi_ctrl_t *const p_api_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_RSPI_Write (spi_ctrl_t *const p_api_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_RSPI_WriteRead (spi_ctrl_t *const p_api_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_RSPI_Close (spi_ctrl_t *const p_api_ctrl)
fsp_err_t	R_RSPI_CalculateBitrate (uint32_t bitrate, rspi_rspck_div_setting_t *spck_div)
fsp_err_t	R_RSPI_CallbackSet (spi_ctrl_t *const p_api_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory)
fsp_err_t	R_RTC_Open (rtc_ctrl_t *const p_ctrl, rtc_cfg_t const *const p_cfg)
fsp_err_t	R_RTC_Close (rtc_ctrl_t *const p_ctrl)
fsp_err_t	R_RTC_ClockSourceSet (rtc_ctrl_t *const p_ctrl)
fsp_err_t	R_RTC_CalendarTimeSet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time)
fsp_err_t	R_RTC_CalendarTimeGet (rtc_ctrl_t *const p_ctrl, rtc_time_t *const p_time)
fsp_err_t	R_RTC_CalendarAlarmSet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm)
fsp_err_t	R_RTC_CalendarAlarmGet (rtc_ctrl_t *const p_ctrl, rtc_alarm_time_t *const p_alarm)
fsp_err_t	R_RTC_PeriodicIrqRateSet (rtc_ctrl_t *const p_ctrl, rtc_periodic_irq_select_t const rate)
fsp_err_t	R_RTC_ErrorAdjustmentSet (rtc_ctrl_t *const p_ctrl, rtc_error_adjustment_cfg_t const *const err_adj_cfg)
fsp_err_t	R_RTC_InfoGet (rtc_ctrl_t *const p_ctrl, rtc_info_t *const p_rtc_info)
fsp_err_t	R_RTC_CallbackSet (rtc_ctrl_t *const p_ctrl, void(*p_callback)(rtc_callback_args_t *), void *const p_context, rtc_callback_args_t *const p_callback_memory)
fsp_err_t	R_RTC_TimeCaptureSet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture)
fsp_err_t	R_RTC_TimeCaptureGet (rtc_ctrl_t *const p_ctrl, rtc_time_capture_t *const p_time_capture)
fsp_err_t	R_SCI_B_I2C_Open (i2c_master_ctrl_t *const p_api_ctrl, i2c_master_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_B_I2C_Close (i2c_master_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_B_I2C_Read (i2c_master_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes, bool const restart)
fsp_err_t	R_SCI_B_I2C_Write (i2c_master_ctrl_t *const p_api_ctrl, uint8_t *const p_src, uint32_t const bytes, bool const restart)
fsp_err_t	R_SCI_B_I2C_Abort (i2c_master_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_B_I2C_SlaveAddressSet (i2c_master_ctrl_t *const p_api_ctrl, uint32_t const slave, i2c_master_addr_mode_t const addr_mode)
fsp_err_t	R_SCI_B_I2C_CallbackSet (i2c_master_ctrl_t *const p_api_ctrl, void(*p_callback)(i2c_master_callback_args_t *), void *const p_context, i2c_master_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_B_I2C_StatusGet (i2c_master_ctrl_t *const p_api_ctrl, i2c_master_status_t *p_status)
fsp_err_t	R_SCI_B_SPI_Open (spi_ctrl_t *p_api_ctrl, spi_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_B_SPI_Read (spi_ctrl_t *const p_api_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_B_SPI_Write (spi_ctrl_t *const p_api_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_B_SPI_WriteRead (spi_ctrl_t *const p_api_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SCI_B_SPI_Close (spi_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_B_SPI_CalculateBitrate (uint32_t bitrate, sci_b_spi_clock_source_t clock_source, sci_b_spi_div_setting_t *sclk_div)
fsp_err_t	R_SCI_B_SPI_CallbackSet (spi_ctrl_t *const p_api_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_B_UART_Open (uart_ctrl_t *const p_api_ctrl, uart_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_B_UART_Read (uart_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCI_B_UART_Write (uart_ctrl_t *const p_api_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCI_B_UART_BaudSet (uart_ctrl_t *const p_api_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCI_B_UART_InfoGet (uart_ctrl_t *const p_api_ctrl, uart_info_t *const p_info)
fsp_err_t	R_SCI_B_UART_Close (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_B_UART_Abort (uart_ctrl_t *const p_api_ctrl, uart_dir_t communication_to_abort)
fsp_err_t	R_SCI_B_UART_BaudCalculate (uint32_t baudrate, bool bitrate_modulation, uint32_t baud_rate_error_x_1000, sci_b_baud_setting_t *const p_baud_setting)
fsp_err_t	R_SCI_B_UART_CallbackSet (uart_ctrl_t *const p_api_ctrl, void(*p_callback)(uart_callback_args_t *), void *const p_context, uart_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_B_UART_ReadStop (uart_ctrl_t *const p_api_ctrl, uint32_t *remaining_bytes)
fsp_err_t	R_SCI_B_UART_ReceiveSuspend (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_B_UART_ReceiveResume (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_UART_Open (uart_ctrl_t *const p_api_ctrl, uart_cfg_t const *const p_cfg)
fsp_err_t	R_SCI_UART_Read (uart_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCI_UART_Write (uart_ctrl_t *const p_api_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCI_UART_BaudSet (uart_ctrl_t *const p_api_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCI_UART_InfoGet (uart_ctrl_t *const p_api_ctrl, uart_info_t *const p_info)
fsp_err_t	R_SCI_UART_Close (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_UART_Abort (uart_ctrl_t *const p_api_ctrl, uart_dir_t communication_to_abort)
fsp_err_t	R_SCI_UART_BaudCalculate (uint32_t baudrate, bool bitrate_modulation, uint32_t baud_rate_error_x_1000, baud_setting_t *const p_baud_setting)
fsp_err_t	R_SCI_UART_CallbackSet (uart_ctrl_t *const p_api_ctrl, void(*p_callback)(uart_callback_args_t *), void *const p_context, uart_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCI_UART_ReadStop (uart_ctrl_t *const p_api_ctrl, uint32_t *remaining_bytes)
fsp_err_t	R_SCI_UART_ReceiveSuspend (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCI_UART_ReceiveResume (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCIF_UART_Open (uart_ctrl_t *const p_api_ctrl, uart_cfg_t const *const p_cfg)
fsp_err_t	R_SCIF_UART_Read (uart_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_SCIF_UART_Write (uart_ctrl_t *const p_api_ctrl, uint8_t const *const p_src, uint32_t const bytes)
fsp_err_t	R_SCIF_UART_BaudSet (uart_ctrl_t *const p_api_ctrl, void const *const p_baud_setting)
fsp_err_t	R_SCIF_UART_InfoGet (uart_ctrl_t *const p_api_ctrl, uart_info_t *const p_info)
fsp_err_t	R_SCIF_UART_Close (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCIF_UART_Abort (uart_ctrl_t *const p_api_ctrl, uart_dir_t communication_to_abort)
fsp_err_t	R_SCIF_UART_BaudCalculate (uart_ctrl_t *const p_api_ctrl, uint32_t baudrate, bool bitrate_modulation, uint32_t baud_rate_error_x_1000, scif_baud_setting_t *const p_baud_setting)
fsp_err_t	R_SCIF_UART_ReadStop (uart_ctrl_t *const p_api_ctrl, uint32_t *remaining_bytes)
fsp_err_t	R_SCIF_UART_ReceiveSuspend (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SCIF_UART_ReceiveResume (uart_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SPI_B_Open (spi_ctrl_t *p_api_ctrl, spi_cfg_t const *const p_cfg)
fsp_err_t	R_SPI_B_Read (spi_ctrl_t *const p_api_ctrl, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_B_Write (spi_ctrl_t *const p_api_ctrl, void const *p_src, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_B_WriteRead (spi_ctrl_t *const p_api_ctrl, void const *p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)
fsp_err_t	R_SPI_B_Close (spi_ctrl_t *const p_api_ctrl)
fsp_err_t	R_SPI_B_CalculateBitrate (uint32_t bitrate, spi_b_clock_source_t clock_source, rspck_div_setting_t *spck_div)
fsp_err_t	R_SPI_B_CallbackSet (spi_ctrl_t *const p_api_ctrl, void(*p_callback)(spi_callback_args_t *), void *const p_context, spi_callback_args_t *const p_callback_memory)
fsp_err_t	R_TSU_B_Open (adc_ctrl_t *p_ctrl, adc_cfg_t const *const p_cfg)
fsp_err_t	R_TSU_B_ScanCfg (adc_ctrl_t *p_ctrl, void const *const p_channel_cfg)
fsp_err_t	R_TSU_B_ScanStart (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_ScanGroupStart (adc_ctrl_t *p_ctrl, adc_group_mask_t group_id)
fsp_err_t	R_TSU_B_ScanStop (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_StatusGet (adc_ctrl_t *p_ctrl, adc_status_t *p_status)
fsp_err_t	R_TSU_B_Read (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint16_t *const p_data)
fsp_err_t	R_TSU_B_Read32 (adc_ctrl_t *p_ctrl, adc_channel_t const reg_id, uint32_t *const p_data)
fsp_err_t	R_TSU_B_Close (adc_ctrl_t *p_ctrl)
fsp_err_t	R_TSU_B_InfoGet (adc_ctrl_t *p_ctrl, adc_info_t *p_adc_info)
fsp_err_t	R_TSU_B_Calibrate (adc_ctrl_t *const p_ctrl, void const *p_extend)
fsp_err_t	R_TSU_B_OffsetSet (adc_ctrl_t *const p_ctrl, adc_channel_t const reg_id, int32_t offset)
fsp_err_t	R_TSU_B_CallbackSet (adc_ctrl_t *const p_api_ctrl, void(*p_callback)(adc_callback_args_t *), void *const p_context, adc_callback_args_t *const p_callback_memory)
fsp_err_t	R_TSU_B_CalculateTemperature (adc_ctrl_t *p_ctrl, uint16_t temperature_code, float *const p_temperature)
fsp_err_t	R_WDT_Refresh (wdt_ctrl_t *const p_ctrl)
fsp_err_t	R_WDT_Open (wdt_ctrl_t *const p_ctrl, wdt_cfg_t const *const p_cfg)
fsp_err_t	R_WDT_StatusClear (wdt_ctrl_t *const p_ctrl, const wdt_status_t status)
fsp_err_t	R_WDT_StatusGet (wdt_ctrl_t *const p_ctrl, wdt_status_t *const p_status)
fsp_err_t	R_WDT_CounterGet (wdt_ctrl_t *const p_ctrl, uint32_t *const p_count)
fsp_err_t	R_WDT_TimeoutGet (wdt_ctrl_t *const p_ctrl, wdt_timeout_values_t *const p_timeout)
fsp_err_t	R_WDT_CallbackSet (wdt_ctrl_t *const p_ctrl, void(*p_callback)(wdt_callback_args_t *), void *const p_context, wdt_callback_args_t *const p_callback_memory)
fsp_err_t	R_XSPI_QSPI_Open (spi_flash_ctrl_t *p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_XSPI_QSPI_Close (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_XSPI_QSPI_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_XSPI_QSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_XSPI_QSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_XipExit (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	R_XSPI_QSPI_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_XSPI_QSPI_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_XSPI_QSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
fsp_err_t	R_XSPI_QSPI_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_XSPI_QSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)
fsp_err_t	RM_COMMS_I2C_Open (rm_comms_ctrl_t *const p_api_ctrl, rm_comms_cfg_t const *const p_cfg)
	Opens and configures the Communications Middle module. Implements rm_comms_api_t::open. More...
fsp_err_t	RM_COMMS_I2C_Close (rm_comms_ctrl_t *const p_api_ctrl)
	Disables specified Communications Middle module. Implements rm_comms_api_t::close. More...
fsp_err_t	RM_COMMS_I2C_Read (rm_comms_ctrl_t *const p_api_ctrl, uint8_t *const p_dest, uint32_t const bytes)
	Performs a read from the I2C device. Implements rm_comms_api_t::read. More...
fsp_err_t	RM_COMMS_I2C_Write (rm_comms_ctrl_t *const p_api_ctrl, uint8_t *const p_src, uint32_t const bytes)
	Performs a write from the I2C device. Implements rm_comms_api_t::write. More...
fsp_err_t	RM_COMMS_I2C_WriteRead (rm_comms_ctrl_t *const p_api_ctrl, rm_comms_write_read_params_t const write_read_params)
	Performs a write to, then a read from the I2C device. Implements rm_comms_api_t::writeRead. More...
void	Reset_Handler_NS (void)
void	Default_Handler (void)
void	NMI_Handler_NS (void)
void	SVC_Handler_NS (void)
	SVC Handler.
void	PendSV_Handler_NS (void)
	PendSV Exception handler.
void	Reset_Handler_S (void)
void	Default_Handler_S (void)
void	NMI_Handler_S (void)
void	SecureFault_Handler (void)
void	SystemInit (void)
void	R_BSP_WarmStart (bsp_warm_start_event_t event)
void	R_BSP_SecurityInit (void)
void	SystemInit_S (void)
void	Warm_Reset_S (void)
void	Entry_Function_S (void)
void	XSPI_Boot_Entry (void)
void	SystemCoreClockUpdate (void)
void	bsp_clock_init (void)
void	bsp_clock_freq_init_cfg (void)
void	bsp_prv_clock_selector_set (fsp_priv_clock_selector_t selector, uint32_t clock_sel)
void	bsp_prv_clock_divider_set (fsp_priv_clock_divider_t divider, uint32_t clock_div)
uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)
fsp_err_t	R_BSP_ClockSelectorSet (fsp_priv_clock_selector_t selector, uint32_t clock_sel)
fsp_err_t	R_BSP_ClockDividerSet (fsp_priv_clock_divider_t divider, uint32_t clock_div)
__STATIC_INLINE IRQn_Type	R_FSP_CurrentIrqGet (void)
__STATIC_INLINE bsp_unique_id_t const *	R_BSP_UniqueIdGet ()
void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)
fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))
__STATIC_INLINE uint32_t	R_BSP_PinRead (bsp_io_port_pin_t pin)
__STATIC_INLINE void	R_BSP_PinWrite (bsp_io_port_pin_t pin, bsp_io_level_t level)
__STATIC_INLINE void	R_BSP_PinAccessEnable (void)
__STATIC_INLINE void	R_BSP_PinAccessDisable (void)
__STATIC_INLINE void	R_BSP_OENAccessEnable (void)
__STATIC_INLINE void	R_BSP_OENAccessDisable (void)
__STATIC_INLINE void	R_BSP_EthernetModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_mode_t mode)
__STATIC_INLINE void	R_BSP_SDVoltageModeCfg (bsp_sd_channel_t channel, bsp_sd_voltage_t voltage)
__STATIC_INLINE void	R_BSP_QSPIVoltageModeCfg (bsp_qspi_voltage_t voltage)
__STATIC_INLINE void	R_BSP_XSPIVoltageModeCfg (bsp_xspi_voltage_t voltage)
__STATIC_INLINE void	R_BSP_EthernetVoltageModeCfg (bsp_ethernet_channel_t channel, bsp_ethernet_voltage_t voltage)
__STATIC_INLINE void	R_BSP_I3CControlCfg (bsp_i3c_voltage_t voltage, bsp_i3c_mode_t mode)
__STATIC_INLINE void	R_BSP_BypassModeCfg (bsp_bypass_oscillator_t oscillator, bsp_bypass_mode_t mode, bsp_bypass_freq_range_t freq_range)
__STATIC_INLINE void	R_BSP_XSPIOutputEnableCfg (void)
void	R_BSP_IrqStatusClear (IRQn_Type irq)
void	R_BSP_IrqClearPending (IRQn_Type irq)
void	R_BSP_IrqCfg (IRQn_Type const irq, uint32_t priority, void *p_context)
void	R_BSP_IrqEnableNoClear (IRQn_Type const irq)
void	R_BSP_IrqEnable (IRQn_Type const irq)
void	R_BSP_IrqDisable (IRQn_Type const irq)
void	R_BSP_IrqCfgEnable (IRQn_Type const irq, uint32_t priority, void *p_context)
void	bsp_irq_cfg (void)
void	bsp_irq_cfg_s (void)
void	R_BSP_NonSecureEnter (void)
fsp_err_t	R_GTM_CallbackSet (timer_ctrl_t *const p_api_ctrl, void(*p_callback)(timer_callback_args_t *), void *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_SCIF_UART_CallbackSet (uart_ctrl_t *const p_api_ctrl, void(*p_callback)(uart_callback_args_t *), void *const p_context, uart_callback_args_t *const p_callback_memory)

Variables
uint32_t SystemCoreClock	BSP_SECTION_EARLY_INIT

Detailed Description

Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file.

Enumeration Type Documentation

dmac_b_external_detection_t [1/3]

enum dmac_b_external_detection_t

Detection method of the external DMA request signal.

Enumerator
DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_EXTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE	Falling/Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.

transfer_event_t [1/4]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [1/4]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [1/4]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

transfer_addr_mode_t [1/4]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

canfd_tx_buffer_t [1/4]

enum canfd_tx_buffer_t

CANFD Transmit Buffer (MB + CFIFO)

canfd_tx_mb_t [1/4]

enum canfd_tx_mb_t

CANFD Transmit Message Buffer (TX MB)

bsp_io_port_t [1/3]

enum bsp_io_port_t

Superset list of all possible IO ports.

Enumerator
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_23	IO port 23.
BSP_IO_PORT_24	IO port 24.
BSP_IO_PORT_25	IO port 25.
BSP_IO_PORT_26	IO port 26.
BSP_IO_PORT_27	IO port 27.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_29	IO port 29.
BSP_IO_PORT_30	IO port 30.
BSP_IO_PORT_31	IO port 31.
BSP_IO_PORT_32	IO port 32.
BSP_IO_PORT_33	IO port 33.
BSP_IO_PORT_34	IO port 34.
BSP_IO_PORT_35	IO port 35.
BSP_IO_PORT_36	IO port 36.
BSP_IO_PORT_37	IO port 37.
BSP_IO_PORT_38	IO port 38.
BSP_IO_PORT_39	IO port 39.
BSP_IO_PORT_40	IO port 40.
BSP_IO_PORT_41	IO port 41.
BSP_IO_PORT_42	IO port 42.
BSP_IO_PORT_43	IO port 43.
BSP_IO_PORT_44	IO port 44.
BSP_IO_PORT_45	IO port 45.
BSP_IO_PORT_46	IO port 46.
BSP_IO_PORT_47	IO port 47.
BSP_IO_PORT_48	IO port 48.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.

bsp_io_port_pin_t [1/3]

enum bsp_io_port_pin_t

Superset list of all possible IO port pins.

Enumerator
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_23_PIN_00	IO port 23 pin 0.
BSP_IO_PORT_23_PIN_01	IO port 23 pin 1.
BSP_IO_PORT_24_PIN_00	IO port 24 pin 0.
BSP_IO_PORT_24_PIN_01	IO port 24 pin 1.
BSP_IO_PORT_25_PIN_00	IO port 25 pin 0.
BSP_IO_PORT_25_PIN_01	IO port 25 pin 1.
BSP_IO_PORT_26_PIN_00	IO port 26 pin 0.
BSP_IO_PORT_26_PIN_01	IO port 26 pin 1.
BSP_IO_PORT_27_PIN_00	IO port 27 pin 0.
BSP_IO_PORT_27_PIN_01	IO port 27 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_29_PIN_00	IO port 29 pin 0.
BSP_IO_PORT_29_PIN_01	IO port 29 pin 1.
BSP_IO_PORT_30_PIN_00	IO port 30 pin 0.
BSP_IO_PORT_30_PIN_01	IO port 30 pin 1.
BSP_IO_PORT_31_PIN_00	IO port 31 pin 0.
BSP_IO_PORT_31_PIN_01	IO port 31 pin 1.
BSP_IO_PORT_32_PIN_00	IO port 32 pin 0.
BSP_IO_PORT_32_PIN_01	IO port 32 pin 1.
BSP_IO_PORT_33_PIN_00	IO port 33 pin 0.
BSP_IO_PORT_33_PIN_01	IO port 33 pin 1.
BSP_IO_PORT_34_PIN_00	IO port 34 pin 0.
BSP_IO_PORT_34_PIN_01	IO port 34 pin 1.
BSP_IO_PORT_35_PIN_00	IO port 35 pin 0.
BSP_IO_PORT_35_PIN_01	IO port 35 pin 1.
BSP_IO_PORT_36_PIN_00	IO port 36 pin 0.
BSP_IO_PORT_36_PIN_01	IO port 36 pin 1.
BSP_IO_PORT_37_PIN_00	IO port 37 pin 0.
BSP_IO_PORT_37_PIN_01	IO port 37 pin 1.
BSP_IO_PORT_37_PIN_02	IO port 37 pin 2.
BSP_IO_PORT_38_PIN_00	IO port 38 pin 0.
BSP_IO_PORT_38_PIN_01	IO port 38 pin 1.
BSP_IO_PORT_39_PIN_00	IO port 39 pin 0.
BSP_IO_PORT_39_PIN_01	IO port 39 pin 1.
BSP_IO_PORT_39_PIN_02	IO port 39 pin 2.
BSP_IO_PORT_40_PIN_00	IO port 40 pin 0.
BSP_IO_PORT_40_PIN_01	IO port 40 pin 1.
BSP_IO_PORT_40_PIN_02	IO port 40 pin 2.
BSP_IO_PORT_41_PIN_00	IO port 41 pin 0.
BSP_IO_PORT_41_PIN_01	IO port 41 pin 1.
BSP_IO_PORT_42_PIN_00	IO port 42 pin 0.
BSP_IO_PORT_42_PIN_01	IO port 42 pin 1.
BSP_IO_PORT_42_PIN_02	IO port 42 pin 2.
BSP_IO_PORT_42_PIN_03	IO port 42 pin 3.
BSP_IO_PORT_42_PIN_04	IO port 42 pin 4.
BSP_IO_PORT_43_PIN_00	IO port 43 pin 0.
BSP_IO_PORT_43_PIN_01	IO port 43 pin 1.
BSP_IO_PORT_43_PIN_02	IO port 43 pin 2.
BSP_IO_PORT_43_PIN_03	IO port 43 pin 3.
BSP_IO_PORT_44_PIN_00	IO port 44 pin 0.
BSP_IO_PORT_44_PIN_01	IO port 44 pin 1.
BSP_IO_PORT_44_PIN_02	IO port 44 pin 2.
BSP_IO_PORT_44_PIN_03	IO port 44 pin 3.
BSP_IO_PORT_45_PIN_00	IO port 45 pin 0.
BSP_IO_PORT_45_PIN_01	IO port 45 pin 1.
BSP_IO_PORT_45_PIN_02	IO port 45 pin 2.
BSP_IO_PORT_45_PIN_03	IO port 45 pin 3.
BSP_IO_PORT_46_PIN_00	IO port 46 pin 0.
BSP_IO_PORT_46_PIN_01	IO port 46 pin 1.
BSP_IO_PORT_46_PIN_02	IO port 46 pin 2.
BSP_IO_PORT_46_PIN_03	IO port 46 pin 3.
BSP_IO_PORT_47_PIN_00	IO port 47 pin 0.
BSP_IO_PORT_47_PIN_01	IO port 47 pin 1.
BSP_IO_PORT_47_PIN_02	IO port 47 pin 2.
BSP_IO_PORT_47_PIN_03	IO port 47 pin 3.
BSP_IO_PORT_48_PIN_00	IO port 48 pin 0.
BSP_IO_PORT_48_PIN_01	IO port 48 pin 1.
BSP_IO_PORT_48_PIN_02	IO port 48 pin 2.
BSP_IO_PORT_48_PIN_03	IO port 48 pin 3.
BSP_IO_PORT_48_PIN_04	IO port 48 pin 4.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI1_SPCLK	QSPI1_SPCLK.
BSP_IO_QSPI1_IO0	QSPI1_IO0.
BSP_IO_QSPI1_IO1	QSPI1_IO1.
BSP_IO_QSPI1_IO2	QSPI1_IO2.
BSP_IO_QSPI1_IO3	QSPI1_IO3.
BSP_IO_QSPI1_SSL	QSPI1_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_QSPI_INT_N	QSPI_INT_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.

bsp_system_reset_signal_t [1/3]

enum bsp_system_reset_signal_t

BSP System Reset Signals

Enumerator
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55	WDT for Cortex-A55.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_0	WDT_Other_0_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_1	WDT_Other_1_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_BUS_ERR_INT	BUS_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_RAM_ERR_INT	RAM_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_0	ACPU_nFAULTIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_1	ACPU_nFAULTIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_2	ACPU_nFAULTIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_3	ACPU_nFAULTIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_4	ACPU_nFAULTIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_0	ACPU_nERRIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_1	ACPU_nERRIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_2	ACPU_nERRIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_3	ACPU_nERRIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_4	ACPU_nERRIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_MCPU_LOCKUP	MCPU_LOCKUP.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_0	GPT_U0_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_1	GPT_U0_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_2	GPT_U0_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_3	GPT_U0_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_4	GPT_U0_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_5	GPT_U0_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_6	GPT_U0_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_7	GPT_U0_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_0	GPT_U0_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_1	GPT_U0_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_2	GPT_U0_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_3	GPT_U0_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_4	GPT_U0_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_5	GPT_U0_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_6	GPT_U0_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_7	GPT_U0_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_0	GPT_U0_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_1	GPT_U0_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_2	GPT_U0_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_3	GPT_U0_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_4	GPT_U0_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_5	GPT_U0_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_6	GPT_U0_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_7	GPT_U0_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_0	GPT_U1_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_1	GPT_U1_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_2	GPT_U1_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_3	GPT_U1_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_4	GPT_U1_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_5	GPT_U1_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_6	GPT_U1_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_7	GPT_U1_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_0	GPT_U1_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_1	GPT_U1_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_2	GPT_U1_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_3	GPT_U1_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_4	GPT_U1_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_5	GPT_U1_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_6	GPT_U1_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_7	GPT_U1_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_0	GPT_U1_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_1	GPT_U1_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_2	GPT_U1_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_3	GPT_U1_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_4	GPT_U1_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_5	GPT_U1_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_6	GPT_U1_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_7	GPT_U1_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_ADC_ada_adereq_n	ADC_ada_adereq_n.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33_FPU	WDT for Cortex-M33_FPU.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.

dmac_b_external_detection_t [2/3]

enum dmac_b_external_detection_t

Detection method of the external DMA request signal.

Enumerator
DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_EXTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE	Falling/Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.

fsp_acc_control_ip_t [1/3]

enum fsp_acc_control_ip_t

access control.

transfer_event_t [2/4]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [2/4]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [2/4]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

transfer_addr_mode_t [2/4]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

canfd_tx_buffer_t [2/4]

enum canfd_tx_buffer_t

CANFD Transmit Buffer (MB + CFIFO)

canfd_tx_mb_t [2/4]

enum canfd_tx_mb_t

CANFD Transmit Message Buffer (TX MB)

bsp_io_port_t [2/3]

enum bsp_io_port_t

Superset list of all possible IO ports.

Enumerator
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_23	IO port 23.
BSP_IO_PORT_24	IO port 24.
BSP_IO_PORT_25	IO port 25.
BSP_IO_PORT_26	IO port 26.
BSP_IO_PORT_27	IO port 27.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_29	IO port 29.
BSP_IO_PORT_30	IO port 30.
BSP_IO_PORT_31	IO port 31.
BSP_IO_PORT_32	IO port 32.
BSP_IO_PORT_33	IO port 33.
BSP_IO_PORT_34	IO port 34.
BSP_IO_PORT_35	IO port 35.
BSP_IO_PORT_36	IO port 36.
BSP_IO_PORT_37	IO port 37.
BSP_IO_PORT_38	IO port 38.
BSP_IO_PORT_39	IO port 39.
BSP_IO_PORT_40	IO port 40.
BSP_IO_PORT_41	IO port 41.
BSP_IO_PORT_42	IO port 42.
BSP_IO_PORT_43	IO port 43.
BSP_IO_PORT_44	IO port 44.
BSP_IO_PORT_45	IO port 45.
BSP_IO_PORT_46	IO port 46.
BSP_IO_PORT_47	IO port 47.
BSP_IO_PORT_48	IO port 48.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.

bsp_io_port_pin_t [2/3]

enum bsp_io_port_pin_t

Superset list of all possible IO port pins.

Enumerator
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_23_PIN_00	IO port 23 pin 0.
BSP_IO_PORT_23_PIN_01	IO port 23 pin 1.
BSP_IO_PORT_24_PIN_00	IO port 24 pin 0.
BSP_IO_PORT_24_PIN_01	IO port 24 pin 1.
BSP_IO_PORT_25_PIN_00	IO port 25 pin 0.
BSP_IO_PORT_25_PIN_01	IO port 25 pin 1.
BSP_IO_PORT_26_PIN_00	IO port 26 pin 0.
BSP_IO_PORT_26_PIN_01	IO port 26 pin 1.
BSP_IO_PORT_27_PIN_00	IO port 27 pin 0.
BSP_IO_PORT_27_PIN_01	IO port 27 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_29_PIN_00	IO port 29 pin 0.
BSP_IO_PORT_29_PIN_01	IO port 29 pin 1.
BSP_IO_PORT_30_PIN_00	IO port 30 pin 0.
BSP_IO_PORT_30_PIN_01	IO port 30 pin 1.
BSP_IO_PORT_31_PIN_00	IO port 31 pin 0.
BSP_IO_PORT_31_PIN_01	IO port 31 pin 1.
BSP_IO_PORT_32_PIN_00	IO port 32 pin 0.
BSP_IO_PORT_32_PIN_01	IO port 32 pin 1.
BSP_IO_PORT_33_PIN_00	IO port 33 pin 0.
BSP_IO_PORT_33_PIN_01	IO port 33 pin 1.
BSP_IO_PORT_34_PIN_00	IO port 34 pin 0.
BSP_IO_PORT_34_PIN_01	IO port 34 pin 1.
BSP_IO_PORT_35_PIN_00	IO port 35 pin 0.
BSP_IO_PORT_35_PIN_01	IO port 35 pin 1.
BSP_IO_PORT_36_PIN_00	IO port 36 pin 0.
BSP_IO_PORT_36_PIN_01	IO port 36 pin 1.
BSP_IO_PORT_37_PIN_00	IO port 37 pin 0.
BSP_IO_PORT_37_PIN_01	IO port 37 pin 1.
BSP_IO_PORT_37_PIN_02	IO port 37 pin 2.
BSP_IO_PORT_38_PIN_00	IO port 38 pin 0.
BSP_IO_PORT_38_PIN_01	IO port 38 pin 1.
BSP_IO_PORT_39_PIN_00	IO port 39 pin 0.
BSP_IO_PORT_39_PIN_01	IO port 39 pin 1.
BSP_IO_PORT_39_PIN_02	IO port 39 pin 2.
BSP_IO_PORT_40_PIN_00	IO port 40 pin 0.
BSP_IO_PORT_40_PIN_01	IO port 40 pin 1.
BSP_IO_PORT_40_PIN_02	IO port 40 pin 2.
BSP_IO_PORT_41_PIN_00	IO port 41 pin 0.
BSP_IO_PORT_41_PIN_01	IO port 41 pin 1.
BSP_IO_PORT_42_PIN_00	IO port 42 pin 0.
BSP_IO_PORT_42_PIN_01	IO port 42 pin 1.
BSP_IO_PORT_42_PIN_02	IO port 42 pin 2.
BSP_IO_PORT_42_PIN_03	IO port 42 pin 3.
BSP_IO_PORT_42_PIN_04	IO port 42 pin 4.
BSP_IO_PORT_43_PIN_00	IO port 43 pin 0.
BSP_IO_PORT_43_PIN_01	IO port 43 pin 1.
BSP_IO_PORT_43_PIN_02	IO port 43 pin 2.
BSP_IO_PORT_43_PIN_03	IO port 43 pin 3.
BSP_IO_PORT_44_PIN_00	IO port 44 pin 0.
BSP_IO_PORT_44_PIN_01	IO port 44 pin 1.
BSP_IO_PORT_44_PIN_02	IO port 44 pin 2.
BSP_IO_PORT_44_PIN_03	IO port 44 pin 3.
BSP_IO_PORT_45_PIN_00	IO port 45 pin 0.
BSP_IO_PORT_45_PIN_01	IO port 45 pin 1.
BSP_IO_PORT_45_PIN_02	IO port 45 pin 2.
BSP_IO_PORT_45_PIN_03	IO port 45 pin 3.
BSP_IO_PORT_46_PIN_00	IO port 46 pin 0.
BSP_IO_PORT_46_PIN_01	IO port 46 pin 1.
BSP_IO_PORT_46_PIN_02	IO port 46 pin 2.
BSP_IO_PORT_46_PIN_03	IO port 46 pin 3.
BSP_IO_PORT_47_PIN_00	IO port 47 pin 0.
BSP_IO_PORT_47_PIN_01	IO port 47 pin 1.
BSP_IO_PORT_47_PIN_02	IO port 47 pin 2.
BSP_IO_PORT_47_PIN_03	IO port 47 pin 3.
BSP_IO_PORT_48_PIN_00	IO port 48 pin 0.
BSP_IO_PORT_48_PIN_01	IO port 48 pin 1.
BSP_IO_PORT_48_PIN_02	IO port 48 pin 2.
BSP_IO_PORT_48_PIN_03	IO port 48 pin 3.
BSP_IO_PORT_48_PIN_04	IO port 48 pin 4.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI1_SPCLK	QSPI1_SPCLK.
BSP_IO_QSPI1_IO0	QSPI1_IO0.
BSP_IO_QSPI1_IO1	QSPI1_IO1.
BSP_IO_QSPI1_IO2	QSPI1_IO2.
BSP_IO_QSPI1_IO3	QSPI1_IO3.
BSP_IO_QSPI1_SSL	QSPI1_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_QSPI_INT_N	QSPI_INT_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.

canfd_error_t

enum canfd_error_t

CANFD Error Code

Enumerator
CANFD_ERROR_CHANNEL_BUS	Bus Error.
CANFD_ERROR_CHANNEL_WARNING	Error Warning (TX/RX error count over 0x5F)
CANFD_ERROR_CHANNEL_PASSIVE	Error Passive (TX/RX error count over 0x7F)
CANFD_ERROR_CHANNEL_BUS_OFF_ENTRY	Bus-Off State Entry.
CANFD_ERROR_CHANNEL_BUS_OFF_RECOVERY	Recovery from Bus-Off State.
CANFD_ERROR_CHANNEL_OVERLOAD	Overload.
CANFD_ERROR_CHANNEL_BUS_LOCK	Bus Locked.
CANFD_ERROR_CHANNEL_ARBITRATION_LOSS	Arbitration Lost.
CANFD_ERROR_CHANNEL_STUFF	Stuff Error.
CANFD_ERROR_CHANNEL_FORM	Form Error.
CANFD_ERROR_CHANNEL_ACK	ACK Error.
CANFD_ERROR_CHANNEL_CRC	CRC Error.
CANFD_ERROR_CHANNEL_BIT_RECESSIVE	Bit Error (recessive) Error.
CANFD_ERROR_CHANNEL_BIT_DOMINANT	Bit Error (dominant) Error.
CANFD_ERROR_CHANNEL_ACK_DELIMITER	ACK Delimiter Error.
CANFD_ERROR_GLOBAL_DLC	DLC Error.
CANFD_ERROR_GLOBAL_MESSAGE_LOST	Message Lost.
CANFD_ERROR_GLOBAL_PAYLOAD_OVERFLOW	FD Payload Overflow.
CANFD_ERROR_GLOBAL_TXQ_OVERWRITE	TX Queue Message Overwrite.
CANFD_ERROR_GLOBAL_TXQ_MESSAGE_LOST	TX Queue Message Lost.
CANFD_ERROR_GLOBAL_CH0_SCAN_FAIL	Channel 0 RX Scan Failure.
CANFD_ERROR_GLOBAL_CH1_SCAN_FAIL	Channel 1 RX Scan Failure.
CANFD_ERROR_GLOBAL_CH0_ECC	Channel 0 ECC Error.
CANFD_ERROR_GLOBAL_CH1_ECC	Channel 1 ECC Error.
CANFD_ERROR_CHANNEL_BUS	Bus Error.
CANFD_ERROR_CHANNEL_WARNING	Error Warning (TX/RX error count over 0x5F)
CANFD_ERROR_CHANNEL_PASSIVE	Error Passive (TX/RX error count over 0x7F)
CANFD_ERROR_CHANNEL_BUS_OFF_ENTRY	Bus-Off State Entry.
CANFD_ERROR_CHANNEL_BUS_OFF_RECOVERY	Recovery from Bus-Off State.
CANFD_ERROR_CHANNEL_OVERLOAD	Overload.
CANFD_ERROR_CHANNEL_BUS_LOCK	Bus Locked.
CANFD_ERROR_CHANNEL_ARBITRATION_LOSS	Arbitration Lost.
CANFD_ERROR_CHANNEL_STUFF	Stuff Error.
CANFD_ERROR_CHANNEL_FORM	Form Error.
CANFD_ERROR_CHANNEL_ACK	ACK Error.
CANFD_ERROR_CHANNEL_CRC	CRC Error.
CANFD_ERROR_CHANNEL_BIT_RECESSIVE	Bit Error (recessive) Error.
CANFD_ERROR_CHANNEL_BIT_DOMINANT	Bit Error (dominant) Error.
CANFD_ERROR_CHANNEL_ACK_DELIMITER	ACK Delimiter Error.
CANFD_ERROR_GLOBAL_DLC	DLC Error.
CANFD_ERROR_GLOBAL_MESSAGE_LOST	Message Lost.
CANFD_ERROR_GLOBAL_PAYLOAD_OVERFLOW	FD Payload Overflow.
CANFD_ERROR_GLOBAL_TXQ_OVERWRITE	TX Queue Message Overwrite.
CANFD_ERROR_GLOBAL_TXQ_MESSAGE_LOST	TX Queue Message Lost.
CANFD_ERROR_GLOBAL_CH0_ECC	Channel 0 ECC Error.
CANFD_ERROR_GLOBAL_CH1_ECC	Channel 1 ECC Error.
CANFD_ERROR_GLOBAL_CH2_ECC	Channel 2 ECC Error.
CANFD_ERROR_GLOBAL_CH3_ECC	Channel 3 ECC Error.
CANFD_ERROR_GLOBAL_CH4_ECC	Channel 4 ECC Error.
CANFD_ERROR_GLOBAL_CH5_ECC	Channel 5 ECC Error.

canfd_rx_buffer_t

enum canfd_rx_buffer_t

CANFD Receive Buffer (MB + FIFO)

canfd_rx_fifo_t

enum canfd_rx_fifo_t

CANFD Receive FIFO (RX FIFO)

canfd_rx_mb_t

enum canfd_rx_mb_t

CANFD Receive Message Buffer (RX MB)

canfd_tx_buffer_t [3/4]

enum canfd_tx_buffer_t

CANFD Transmit Buffer (MB + CFIFO)

canfd_tx_mb_t [3/4]

enum canfd_tx_mb_t

CANFD Transmit Message Buffer (TX MB)

fsp_acc_control_ip_t [2/3]

enum fsp_acc_control_ip_t

access control.

fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_GTM	General Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_PORT	I/O Ports.
FSP_IP_IM33	IM33 (Interrupt controller)
FSP_IP_SCIF	Serial Communications Interface with FIFO.
FSP_IP_RIIC	I2C Bus Interface.
FSP_IP_RSPI	Renesas Serial Peripheral Interface.
FSP_IP_MHU	Message Handling Unit.
FSP_IP_DMAC	Direct Memory Access Controller.
FSP_IP_DMAC_s	Direct Memory Access Controller.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_CANFD	CANFD Interface (RS-CANFD)
FSP_IP_ADC	A/D Converter.
FSP_IP_TSU	Thermal Sensor Unit.
FSP_IP_WDT	Watchdog Timer.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_MTU3	Multi-Function Timer Pulse Unit 3.
FSP_IP_XSPI	Expanded Serial Peripheral Interface.
FSP_IP_GTM	General Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_PORT	I/O Ports.
FSP_IP_IM33	IM33 (Interrupt controller)
FSP_IP_SCIF	Serial Communications Interface with FIFO.
FSP_IP_RIIC	I2C Bus Interface.
FSP_IP_RSPI	Renesas Serial Peripheral Interface.
FSP_IP_MHU	Message Handling Unit.
FSP_IP_DMAC	Direct Memory Access Controller.
FSP_IP_DMAC_s	Direct Memory Access Controller.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_CANFD	CANFD Interface (RS-CANFD)
FSP_IP_ADC	A/D Converter.
FSP_IP_TSU	Thermal Sensor Unit.
FSP_IP_WDT	Watchdog Timer.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_CMTW	Compare Match Timer W.
FSP_IP_XSPI	Expanded Serial Peripheral Interface.
FSP_IP_CRC	Cyclic redundancy check (CRC) operation units.
FSP_IP_I3C	I3C Bus Interface.
FSP_IP_RTC	Realtime Clock.
FSP_IP_SYC	System counter.

fsp_mst_acc_control_ip_t [1/2]

enum fsp_mst_acc_control_ip_t

master access control.

bsp_system_reset_signal_t [2/3]

enum bsp_system_reset_signal_t

BSP System Reset Signals

Enumerator
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55	WDT for Cortex-A55.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_0	WDT_Other_0_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_1	WDT_Other_1_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_BUS_ERR_INT	BUS_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_RAM_ERR_INT	RAM_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_0	ACPU_nFAULTIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_1	ACPU_nFAULTIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_2	ACPU_nFAULTIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_3	ACPU_nFAULTIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_4	ACPU_nFAULTIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_0	ACPU_nERRIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_1	ACPU_nERRIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_2	ACPU_nERRIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_3	ACPU_nERRIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_4	ACPU_nERRIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_MCPU_LOCKUP	MCPU_LOCKUP.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_0	GPT_U0_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_1	GPT_U0_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_2	GPT_U0_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_3	GPT_U0_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_4	GPT_U0_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_5	GPT_U0_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_6	GPT_U0_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_7	GPT_U0_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_0	GPT_U0_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_1	GPT_U0_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_2	GPT_U0_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_3	GPT_U0_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_4	GPT_U0_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_5	GPT_U0_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_6	GPT_U0_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_7	GPT_U0_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_0	GPT_U0_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_1	GPT_U0_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_2	GPT_U0_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_3	GPT_U0_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_4	GPT_U0_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_5	GPT_U0_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_6	GPT_U0_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_7	GPT_U0_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_0	GPT_U1_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_1	GPT_U1_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_2	GPT_U1_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_3	GPT_U1_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_4	GPT_U1_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_5	GPT_U1_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_6	GPT_U1_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_7	GPT_U1_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_0	GPT_U1_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_1	GPT_U1_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_2	GPT_U1_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_3	GPT_U1_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_4	GPT_U1_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_5	GPT_U1_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_6	GPT_U1_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_7	GPT_U1_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_0	GPT_U1_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_1	GPT_U1_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_2	GPT_U1_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_3	GPT_U1_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_4	GPT_U1_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_5	GPT_U1_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_6	GPT_U1_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_7	GPT_U1_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_ADC_ada_adereq_n	ADC_ada_adereq_n.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33_FPU	WDT for Cortex-M33_FPU.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.

elc_peripheral_t

enum elc_peripheral_t

Possible peripherals to be linked to event signals (not all available on all MPUs)

elc_software_event_t

enum elc_software_event_t

Software event number

Enumerator
ELC_SOFTWARE_EVENT_0	Software event 0.
ELC_SOFTWARE_EVENT_1	Software event 1.
ELC_SOFTWARE_EVENT_0	Software event 0.
ELC_SOFTWARE_EVENT_1	Software event 1.

gpt_source_t

enum gpt_source_t

Sources can be used to start the timer, stop the timer, count up, or count down. These enumerations represent a bitmask. Multiple sources can be ORed together.

Enumerator
GPT_SOURCE_NONE	No active event sources.
GPT_SOURCE_GTETRGA_RISING	Action performed on GTETRGA rising edge.
GPT_SOURCE_GTETRGA_FALLING	Action performed on GTETRGA falling edge.
GPT_SOURCE_GTETRGB_RISING	Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGB_FALLING	Action performed on GTETRGB falling edge.
GPT_SOURCE_GTETRGC_RISING	Action performed on GTETRGC rising edge.
GPT_SOURCE_GTETRGC_FALLING	Action performed on GTETRGC falling edge.
GPT_SOURCE_GTETRGD_RISING	Action performed on GTETRGD rising edge. Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGD_FALLING	Action performed on GTETRGD falling edge. Action performed on GTETRGB falling edge.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input rises while GTIOCB is low.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input rises while GTIOCB is high.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input falls while GTIOCB is low.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input falls while GTIOCB is high.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input rises while GTIOCA is low.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input rises while GTIOCA is high.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input falls while GTIOCA is low.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input falls while GTIOCA is high.
GPT_SOURCE_GPT_A	Action performed on ELC GPTA event.
GPT_SOURCE_GPT_B	Action performed on ELC GPTB event.
GPT_SOURCE_GPT_C	Action performed on ELC GPTC event.
GPT_SOURCE_GPT_D	Action performed on ELC GPTD event.
GPT_SOURCE_GPT_E	Action performed on ELC GPTE event.
GPT_SOURCE_GPT_F	Action performed on ELC GPTF event.
GPT_SOURCE_GPT_G	Action performed on ELC GPTG event.
GPT_SOURCE_GPT_H	Action performed on ELC GPTH event.
GPT_SOURCE_NONE	No active event sources.
GPT_SOURCE_GTETRGA_RISING	Action performed on GTETRGA rising edge.
GPT_SOURCE_GTETRGA_FALLING	Action performed on GTETRGA falling edge.
GPT_SOURCE_GTETRGB_RISING	Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGB_FALLING	Action performed on GTETRGB falling edge.
GPT_SOURCE_GTETRGC_RISING	Action performed on GTETRGC rising edge.
GPT_SOURCE_GTETRGC_FALLING	Action performed on GTETRGC falling edge.
GPT_SOURCE_GTETRGD_RISING	Action performed on GTETRGD rising edge. Action performed on GTETRGB rising edge.
GPT_SOURCE_GTETRGD_FALLING	Action performed on GTETRGD falling edge. Action performed on GTETRGB falling edge.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input rises while GTIOCB is low.
GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input rises while GTIOCB is high.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW	Action performed when GTIOCA input falls while GTIOCB is low.
GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH	Action performed when GTIOCA input falls while GTIOCB is high.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input rises while GTIOCA is low.
GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input rises while GTIOCA is high.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW	Action performed when GTIOCB input falls while GTIOCA is low.
GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH	Action performed when GTIOCB input falls while GTIOCA is high.
GPT_SOURCE_GPT0_ACT0	Action performed on ELC GPT0 (A) event.
GPT_SOURCE_GPT0_ACT1	Action performed on ELC GPT0 (B) event.
GPT_SOURCE_GPT0_ACT2	Action performed on ELC GPT0 (C) event.
GPT_SOURCE_GPT0_ACT3	Action performed on ELC GPT0 (D) event.
GPT_SOURCE_GPT0_ACT4	Action performed on ELC GPT0 (E) event.
GPT_SOURCE_GPT0_ACT5	Action performed on ELC GPT0 (F) event.
GPT_SOURCE_GPT0_ACT6	Action performed on ELC GPT0 (G) event.
GPT_SOURCE_GPT0_ACT7	Action performed on ELC GPT0 (H) event.
GPT_SOURCE_GPT1_ACT0	Action performed on ELC GPT1 (A) event.
GPT_SOURCE_GPT1_ACT1	Action performed on ELC GPT1 (B) event.
GPT_SOURCE_GPT1_ACT2	Action performed on ELC GPT1 (C) event.
GPT_SOURCE_GPT1_ACT3	Action performed on ELC GPT1 (D) event.
GPT_SOURCE_GPT1_ACT4	Action performed on ELC GPT1 (E) event.
GPT_SOURCE_GPT1_ACT5	Action performed on ELC GPT1 (F) event.
GPT_SOURCE_GPT1_ACT6	Action performed on ELC GPT1 (G) event.
GPT_SOURCE_GPT1_ACT7	Action performed on ELC GPT1 (H) event.

ioport_cfg_options_t

enum ioport_cfg_options_t

Options to configure pin functions.

Enumerator
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z (default)
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input.
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output (input disable)
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (input enable)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PULLUP_PULLDOWN_DISABLE	Disable the pin's internal pull-up and pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's internal pull-down.
IOPORT_CFG_NOD_DISABLE	Disable the pin's N-ch open-drain.
IOPORT_CFG_NOD_ENABLE	Enables the pin's N-ch open-drain.
IOPORT_CFG_SCHMITT_DISABLE	Disable the pin's Schmitt-trigger input.
IOPORT_CFG_SCHMITT_ENABLE	Enables the pin's Schmitt-trigger input.
IOPORT_CFG_DRIVE_B00	Sets the IOLH register value to b'00.
IOPORT_CFG_DRIVE_B01	Sets the IOLH register value to b'01.
IOPORT_CFG_DRIVE_B10	Sets the IOLH register value to b'10.
IOPORT_CFG_DRIVE_B11	Sets the IOLH register value to b'11.
IOPORT_CFG_TINT_DISABLE	Disable IRQ functionality for a pin.
IOPORT_CFG_TINT_ENABLE	Sets pin as an IRQ pin.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the pin slew-rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the pin slew-rate to fast.
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_DISABLE	Disable input the pin of special purpose port.
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_ENABLE	Sets the pin of special purpose port to input.
IOPORT_CFG_NOISE_FILTER_OFF	Noise filter disable.
IOPORT_CFG_NOISE_FILTER_ON	Noise filter enable.
IOPORT_CFG_NOISE_FILTER_NUM_4STAGE	Sets the pin noise filter to 4-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_8STAGE	Sets the pin noise filter to 8-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_12STAGE	Sets the pin noise filter to 12-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_16STAGE	Sets the pin noise filter to 16-stage filter.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B00	Sets the FILCLKSEL register value to b'00.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B01	Sets the FILCLKSEL register value to b'01.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B10	Sets the FILCLKSEL register value to b'10.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B11	Sets the FILCLKSEL register value to b'11.
IOPORT_CFG_PERIPHERAL_PIN	Enables pin to operate as a peripheral pin.
IOPORT_CFG_PORT_DIRECTION_HIZ	Sets the pin direction to Hi-Z (default)
IOPORT_CFG_PORT_DIRECTION_INPUT	Sets the pin direction to input.
IOPORT_CFG_PORT_DIRECTION_OUTPUT	Sets the pin direction to output (input disable)
IOPORT_CFG_PORT_DIRECTION_OUTPUT_INPUT	Sets the pin direction to output (input enable)
IOPORT_CFG_PORT_OUTPUT_LOW	Sets the pin level to low.
IOPORT_CFG_PORT_OUTPUT_HIGH	Sets the pin level to high.
IOPORT_CFG_PULLUP_PULLDOWN_DISABLE	Disable the pin's internal pull-up and pull-down.
IOPORT_CFG_PULLUP_ENABLE	Enables the pin's internal pull-up.
IOPORT_CFG_PULLDOWN_ENABLE	Enables the pin's internal pull-down.
IOPORT_CFG_NOD_DISABLE	Disable the pin's N-ch open-drain.
IOPORT_CFG_NOD_ENABLE	Enables the pin's N-ch open-drain.
IOPORT_CFG_SCHMITT_DISABLE	Disable the pin's Schmitt-trigger input.
IOPORT_CFG_SCHMITT_ENABLE	Enables the pin's Schmitt-trigger input.
IOPORT_CFG_DRIVE_B00	Sets the IOLH register value to b'00.
IOPORT_CFG_DRIVE_B01	Sets the IOLH register value to b'01.
IOPORT_CFG_DRIVE_B10	Sets the IOLH register value to b'10.
IOPORT_CFG_DRIVE_B11	Sets the IOLH register value to b'11.
IOPORT_CFG_TINT_DISABLE	Disable IRQ functionality for a pin.
IOPORT_CFG_TINT_ENABLE	Sets pin as an IRQ pin.
IOPORT_CFG_SLEW_RATE_SLOW	Sets the pin slew-rate to slow.
IOPORT_CFG_SLEW_RATE_FAST	Sets the pin slew-rate to fast.
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_DISABLE	Disable input the pin of special purpose port.
IOPORT_CFG_SPECIAL_PURPOSE_PORT_INPUT_ENABLE	Sets the pin of special purpose port to input.
IOPORT_CFG_NOISE_FILTER_OFF	Noise filter disable.
IOPORT_CFG_NOISE_FILTER_ON	Noise filter enable.
IOPORT_CFG_NOISE_FILTER_NUM_4STAGE	Sets the pin noise filter to 4-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_8STAGE	Sets the pin noise filter to 8-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_12STAGE	Sets the pin noise filter to 12-stage filter.
IOPORT_CFG_NOISE_FILTER_NUM_16STAGE	Sets the pin noise filter to 16-stage filter.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B00	Sets the FILCLKSEL register value to b'00.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B01	Sets the FILCLKSEL register value to b'01.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B10	Sets the FILCLKSEL register value to b'10.
IOPORT_CFG_NOISE_FILTER_DIVIDED_B11	Sets the FILCLKSEL register value to b'11.
IOPORT_CFG_PERIPHERAL_PIN	Enables pin to operate as a peripheral pin.

spi_b_clock_source_t

enum spi_b_clock_source_t

SPI communication clock source.

transfer_event_t [3/4]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [3/4]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [3/4]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

transfer_addr_mode_t [3/4]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

bsp_io_port_t [3/3]

enum bsp_io_port_t

Superset list of all possible IO ports.

Enumerator
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_23	IO port 23.
BSP_IO_PORT_24	IO port 24.
BSP_IO_PORT_25	IO port 25.
BSP_IO_PORT_26	IO port 26.
BSP_IO_PORT_27	IO port 27.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_29	IO port 29.
BSP_IO_PORT_30	IO port 30.
BSP_IO_PORT_31	IO port 31.
BSP_IO_PORT_32	IO port 32.
BSP_IO_PORT_33	IO port 33.
BSP_IO_PORT_34	IO port 34.
BSP_IO_PORT_35	IO port 35.
BSP_IO_PORT_36	IO port 36.
BSP_IO_PORT_37	IO port 37.
BSP_IO_PORT_38	IO port 38.
BSP_IO_PORT_39	IO port 39.
BSP_IO_PORT_40	IO port 40.
BSP_IO_PORT_41	IO port 41.
BSP_IO_PORT_42	IO port 42.
BSP_IO_PORT_43	IO port 43.
BSP_IO_PORT_44	IO port 44.
BSP_IO_PORT_45	IO port 45.
BSP_IO_PORT_46	IO port 46.
BSP_IO_PORT_47	IO port 47.
BSP_IO_PORT_48	IO port 48.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_19	IO port 19.
BSP_IO_PORT_20	IO port 20.
BSP_IO_PORT_21	IO port 21.
BSP_IO_PORT_22	IO port 22.
BSP_IO_PORT_28	IO port 28.
BSP_IO_PORT_00	IO port 0.
BSP_IO_PORT_01	IO port 1.
BSP_IO_PORT_02	IO port 2.
BSP_IO_PORT_03	IO port 3.
BSP_IO_PORT_04	IO port 4.
BSP_IO_PORT_05	IO port 5.
BSP_IO_PORT_06	IO port 6.
BSP_IO_PORT_07	IO port 7.
BSP_IO_PORT_08	IO port 8.
BSP_IO_PORT_09	IO port 9.
BSP_IO_PORT_10	IO port 10.
BSP_IO_PORT_11	IO port 11.
BSP_IO_PORT_12	IO port 12.
BSP_IO_PORT_13	IO port 13.
BSP_IO_PORT_14	IO port 14.
BSP_IO_PORT_15	IO port 15.
BSP_IO_PORT_16	IO port 16.
BSP_IO_PORT_17	IO port 17.
BSP_IO_PORT_18	IO port 18.

bsp_io_port_pin_t [3/3]

enum bsp_io_port_pin_t

Superset list of all possible IO port pins.

Enumerator
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_23_PIN_00	IO port 23 pin 0.
BSP_IO_PORT_23_PIN_01	IO port 23 pin 1.
BSP_IO_PORT_24_PIN_00	IO port 24 pin 0.
BSP_IO_PORT_24_PIN_01	IO port 24 pin 1.
BSP_IO_PORT_25_PIN_00	IO port 25 pin 0.
BSP_IO_PORT_25_PIN_01	IO port 25 pin 1.
BSP_IO_PORT_26_PIN_00	IO port 26 pin 0.
BSP_IO_PORT_26_PIN_01	IO port 26 pin 1.
BSP_IO_PORT_27_PIN_00	IO port 27 pin 0.
BSP_IO_PORT_27_PIN_01	IO port 27 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_29_PIN_00	IO port 29 pin 0.
BSP_IO_PORT_29_PIN_01	IO port 29 pin 1.
BSP_IO_PORT_30_PIN_00	IO port 30 pin 0.
BSP_IO_PORT_30_PIN_01	IO port 30 pin 1.
BSP_IO_PORT_31_PIN_00	IO port 31 pin 0.
BSP_IO_PORT_31_PIN_01	IO port 31 pin 1.
BSP_IO_PORT_32_PIN_00	IO port 32 pin 0.
BSP_IO_PORT_32_PIN_01	IO port 32 pin 1.
BSP_IO_PORT_33_PIN_00	IO port 33 pin 0.
BSP_IO_PORT_33_PIN_01	IO port 33 pin 1.
BSP_IO_PORT_34_PIN_00	IO port 34 pin 0.
BSP_IO_PORT_34_PIN_01	IO port 34 pin 1.
BSP_IO_PORT_35_PIN_00	IO port 35 pin 0.
BSP_IO_PORT_35_PIN_01	IO port 35 pin 1.
BSP_IO_PORT_36_PIN_00	IO port 36 pin 0.
BSP_IO_PORT_36_PIN_01	IO port 36 pin 1.
BSP_IO_PORT_37_PIN_00	IO port 37 pin 0.
BSP_IO_PORT_37_PIN_01	IO port 37 pin 1.
BSP_IO_PORT_37_PIN_02	IO port 37 pin 2.
BSP_IO_PORT_38_PIN_00	IO port 38 pin 0.
BSP_IO_PORT_38_PIN_01	IO port 38 pin 1.
BSP_IO_PORT_39_PIN_00	IO port 39 pin 0.
BSP_IO_PORT_39_PIN_01	IO port 39 pin 1.
BSP_IO_PORT_39_PIN_02	IO port 39 pin 2.
BSP_IO_PORT_40_PIN_00	IO port 40 pin 0.
BSP_IO_PORT_40_PIN_01	IO port 40 pin 1.
BSP_IO_PORT_40_PIN_02	IO port 40 pin 2.
BSP_IO_PORT_41_PIN_00	IO port 41 pin 0.
BSP_IO_PORT_41_PIN_01	IO port 41 pin 1.
BSP_IO_PORT_42_PIN_00	IO port 42 pin 0.
BSP_IO_PORT_42_PIN_01	IO port 42 pin 1.
BSP_IO_PORT_42_PIN_02	IO port 42 pin 2.
BSP_IO_PORT_42_PIN_03	IO port 42 pin 3.
BSP_IO_PORT_42_PIN_04	IO port 42 pin 4.
BSP_IO_PORT_43_PIN_00	IO port 43 pin 0.
BSP_IO_PORT_43_PIN_01	IO port 43 pin 1.
BSP_IO_PORT_43_PIN_02	IO port 43 pin 2.
BSP_IO_PORT_43_PIN_03	IO port 43 pin 3.
BSP_IO_PORT_44_PIN_00	IO port 44 pin 0.
BSP_IO_PORT_44_PIN_01	IO port 44 pin 1.
BSP_IO_PORT_44_PIN_02	IO port 44 pin 2.
BSP_IO_PORT_44_PIN_03	IO port 44 pin 3.
BSP_IO_PORT_45_PIN_00	IO port 45 pin 0.
BSP_IO_PORT_45_PIN_01	IO port 45 pin 1.
BSP_IO_PORT_45_PIN_02	IO port 45 pin 2.
BSP_IO_PORT_45_PIN_03	IO port 45 pin 3.
BSP_IO_PORT_46_PIN_00	IO port 46 pin 0.
BSP_IO_PORT_46_PIN_01	IO port 46 pin 1.
BSP_IO_PORT_46_PIN_02	IO port 46 pin 2.
BSP_IO_PORT_46_PIN_03	IO port 46 pin 3.
BSP_IO_PORT_47_PIN_00	IO port 47 pin 0.
BSP_IO_PORT_47_PIN_01	IO port 47 pin 1.
BSP_IO_PORT_47_PIN_02	IO port 47 pin 2.
BSP_IO_PORT_47_PIN_03	IO port 47 pin 3.
BSP_IO_PORT_48_PIN_00	IO port 48 pin 0.
BSP_IO_PORT_48_PIN_01	IO port 48 pin 1.
BSP_IO_PORT_48_PIN_02	IO port 48 pin 2.
BSP_IO_PORT_48_PIN_03	IO port 48 pin 3.
BSP_IO_PORT_48_PIN_04	IO port 48 pin 4.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI1_SPCLK	QSPI1_SPCLK.
BSP_IO_QSPI1_IO0	QSPI1_IO0.
BSP_IO_QSPI1_IO1	QSPI1_IO1.
BSP_IO_QSPI1_IO2	QSPI1_IO2.
BSP_IO_QSPI1_IO3	QSPI1_IO3.
BSP_IO_QSPI1_SSL	QSPI1_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_QSPI_INT_N	QSPI_INT_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.
BSP_IO_QSPI0_SPCLK	QSPI0_SPCLK.
BSP_IO_QSPI0_IO0	QSPI0_IO0.
BSP_IO_QSPI0_IO1	QSPI0_IO1.
BSP_IO_QSPI0_IO2	QSPI0_IO2.
BSP_IO_QSPI0_IO3	QSPI0_IO3.
BSP_IO_QSPI0_SSL	QSPI0_SSL.
BSP_IO_QSPI_RESET_N	QSPI_RESET_N.
BSP_IO_QSPI_WP_N	QSPI_WP_N.
BSP_IO_WDTOVF_PERROUT_N	WDTOVF_PERROUT_N.
BSP_IO_RIIC0_SDA	RIIC0_SDA.
BSP_IO_RIIC0_SCL	RIIC0_SCL.
BSP_IO_RIIC1_SDA	RIIC1_SDA.
BSP_IO_RIIC1_SCL	RIIC1_SCL.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_19_PIN_00	IO port 19 pin 0.
BSP_IO_PORT_19_PIN_01	IO port 19 pin 1.
BSP_IO_PORT_20_PIN_00	IO port 20 pin 0.
BSP_IO_PORT_20_PIN_01	IO port 20 pin 1.
BSP_IO_PORT_20_PIN_02	IO port 20 pin 2.
BSP_IO_PORT_21_PIN_00	IO port 21 pin 0.
BSP_IO_PORT_21_PIN_01	IO port 21 pin 1.
BSP_IO_PORT_22_PIN_00	IO port 22 pin 0.
BSP_IO_PORT_22_PIN_01	IO port 22 pin 1.
BSP_IO_PORT_28_PIN_00	IO port 28 pin 0.
BSP_IO_PORT_28_PIN_01	IO port 28 pin 1.
BSP_IO_PORT_00_PIN_00	IO port 0 pin 0.
BSP_IO_PORT_00_PIN_01	IO port 0 pin 1.
BSP_IO_PORT_05_PIN_00	IO port 5 pin 0.
BSP_IO_PORT_05_PIN_01	IO port 5 pin 1.
BSP_IO_PORT_05_PIN_02	IO port 5 pin 2.
BSP_IO_PORT_06_PIN_00	IO port 6 pin 0.
BSP_IO_PORT_06_PIN_01	IO port 6 pin 1.
BSP_IO_PORT_11_PIN_00	IO port 11 pin 0.
BSP_IO_PORT_11_PIN_01	IO port 11 pin 1.
BSP_IO_PORT_12_PIN_00	IO port 12 pin 0.
BSP_IO_PORT_12_PIN_01	IO port 12 pin 1.
BSP_IO_PORT_13_PIN_00	IO port 13 pin 0.
BSP_IO_PORT_13_PIN_01	IO port 13 pin 1.
BSP_IO_PORT_13_PIN_02	IO port 13 pin 2.
BSP_IO_PORT_14_PIN_00	IO port 14 pin 0.
BSP_IO_PORT_14_PIN_01	IO port 14 pin 1.
BSP_IO_PORT_15_PIN_00	IO port 15 pin 0.
BSP_IO_PORT_15_PIN_01	IO port 15 pin 1.
BSP_IO_PORT_16_PIN_00	IO port 16 pin 0.
BSP_IO_PORT_16_PIN_01	IO port 16 pin 1.
BSP_IO_PORT_17_PIN_00	IO port 17 pin 0.
BSP_IO_PORT_17_PIN_01	IO port 17 pin 1.
BSP_IO_PORT_17_PIN_02	IO port 17 pin 2.
BSP_IO_PORT_18_PIN_00	IO port 18 pin 0.
BSP_IO_PORT_18_PIN_01	IO port 18 pin 1.
BSP_IO_PORT_01_PIN_00	IO port 1 pin 0.
BSP_IO_PORT_01_PIN_01	IO port 1 pin 1.
BSP_IO_PORT_02_PIN_00	IO port 2 pin 0.
BSP_IO_PORT_02_PIN_01	IO port 2 pin 1.
BSP_IO_PORT_03_PIN_00	IO port 3 pin 0.
BSP_IO_PORT_03_PIN_01	IO port 3 pin 1.
BSP_IO_PORT_04_PIN_00	IO port 4 pin 0.
BSP_IO_PORT_04_PIN_01	IO port 4 pin 1.
BSP_IO_PORT_07_PIN_00	IO port 7 pin 0.
BSP_IO_PORT_07_PIN_01	IO port 7 pin 1.
BSP_IO_PORT_07_PIN_02	IO port 7 pin 2.
BSP_IO_PORT_08_PIN_00	IO port 8 pin 0.
BSP_IO_PORT_08_PIN_01	IO port 8 pin 1.
BSP_IO_PORT_08_PIN_02	IO port 8 pin 2.
BSP_IO_PORT_09_PIN_00	IO port 9 pin 0.
BSP_IO_PORT_09_PIN_01	IO port 9 pin 1.
BSP_IO_PORT_10_PIN_00	IO port 10 pin 0.
BSP_IO_PORT_10_PIN_01	IO port 10 pin 1.
BSP_IO_NMI	NMI.
BSP_IO_TMS_SWDIO	TMS_SWDIO.
BSP_IO_TDO	TDO.
BSP_IO_AUDIO_CLK1	AUDIO_CLK1.
BSP_IO_AUDIO_CLK2	AUDIO_CLK2.
BSP_IO_SD0_CLK	CD0_CLK.
BSP_IO_SD0_CMD	CD0_CMD.
BSP_IO_SD0_RST_N	CD0_RST_N.
BSP_IO_SD0_DATA0	SD0_DATA0.
BSP_IO_SD0_DATA1	SD0_DATA1.
BSP_IO_SD0_DATA2	SD0_DATA2.
BSP_IO_SD0_DATA3	SD0_DATA3.
BSP_IO_SD0_DATA4	SD0_DATA4.
BSP_IO_SD0_DATA5	SD0_DATA5.
BSP_IO_SD0_DATA6	SD0_DATA6.
BSP_IO_SD0_DATA7	SD0_DATA7.
BSP_IO_SD1_CLK	SD1_CLK.
BSP_IO_SD1_CMD	SD1_CMD.
BSP_IO_SD1_DATA0	SD1_DATA0.
BSP_IO_SD1_DATA1	SD1_DATA1.
BSP_IO_SD1_DATA2	SD1_DATA2.
BSP_IO_SD1_DATA3	SD1_DATA3.

bsp_system_reset_signal_t [3/3]

enum bsp_system_reset_signal_t

BSP System Reset Signals

Enumerator
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55	WDT for Cortex-A55.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_0	WDT_Other_0_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_WDT_Other_1	WDT_Other_1_iwdt_nmiundf_n.
BSP_SYSTEM_RESET_SIGNAL_BUS_ERR_INT	BUS_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_RAM_ERR_INT	RAM_ERR_INT.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_0	ACPU_nFAULTIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_1	ACPU_nFAULTIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_2	ACPU_nFAULTIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_3	ACPU_nFAULTIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nFAULTIRQ_4	ACPU_nFAULTIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_0	ACPU_nERRIRQ_0.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_1	ACPU_nERRIRQ_1.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_2	ACPU_nERRIRQ_2.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_3	ACPU_nERRIRQ_3.
BSP_SYSTEM_RESET_SIGNAL_ACPU_nERRIRQ_4	ACPU_nERRIRQ_4.
BSP_SYSTEM_RESET_SIGNAL_MCPU_LOCKUP	MCPU_LOCKUP.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_0	GPT_U0_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_1	GPT_U0_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_2	GPT_U0_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_3	GPT_U0_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_4	GPT_U0_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_5	GPT_U0_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_6	GPT_U0_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciv_n_7	GPT_U0_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_0	GPT_U0_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_1	GPT_U0_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_2	GPT_U0_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_3	GPT_U0_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_4	GPT_U0_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_5	GPT_U0_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_6	GPT_U0_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtciu_n_7	GPT_U0_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_0	GPT_U0_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_1	GPT_U0_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_2	GPT_U0_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_3	GPT_U0_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_4	GPT_U0_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_5	GPT_U0_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_6	GPT_U0_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U0_gpt_gtdei_n_7	GPT_U0_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_0	GPT_U1_gpt_gtciv_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_1	GPT_U1_gpt_gtciv_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_2	GPT_U1_gpt_gtciv_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_3	GPT_U1_gpt_gtciv_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_4	GPT_U1_gpt_gtciv_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_5	GPT_U1_gpt_gtciv_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_6	GPT_U1_gpt_gtciv_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciv_n_7	GPT_U1_gpt_gtciv_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_0	GPT_U1_gpt_gtciu_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_1	GPT_U1_gpt_gtciu_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_2	GPT_U1_gpt_gtciu_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_3	GPT_U1_gpt_gtciu_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_4	GPT_U1_gpt_gtciu_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_5	GPT_U1_gpt_gtciu_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_6	GPT_U1_gpt_gtciu_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtciu_n_7	GPT_U1_gpt_gtciu_n_7.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_0	GPT_U1_gpt_gtdei_n_0.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_1	GPT_U1_gpt_gtdei_n_1.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_2	GPT_U1_gpt_gtdei_n_2.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_3	GPT_U1_gpt_gtdei_n_3.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_4	GPT_U1_gpt_gtdei_n_4.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_5	GPT_U1_gpt_gtdei_n_5.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_6	GPT_U1_gpt_gtdei_n_6.
BSP_SYSTEM_RESET_SIGNAL_GPT_U1_gpt_gtdei_n_7	GPT_U1_gpt_gtdei_n_7.
BSP_SYSTEM_RESET_SIGNAL_ADC_ada_adereq_n	ADC_ada_adereq_n.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.
BSP_SYSTEM_RESET_SIGNAL_WDT_CA55_0	WDT for Cortex-A55 Core 0.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33	WDT for Cortex-M33.
BSP_SYSTEM_RESET_SIGNAL_WDT_CM33_FPU	WDT for Cortex-M33_FPU.
BSP_SYSTEM_RESET_SIGNAL_MAX	The number of supported system reset signals.

canfd_tx_buffer_t [4/4]

enum canfd_tx_buffer_t

CANFD Transmit Buffer (MB + CFIFO)

canfd_tx_mb_t [4/4]

enum canfd_tx_mb_t

CANFD Transmit Message Buffer (TX MB)

dmac_b_external_detection_t [3/3]

enum dmac_b_external_detection_t

Detection method of the external DMA request signal.

Enumerator
DMAC_B_EXTERNAL_DETECTION_LOW_LEVEL	Low level detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_EDGE	Falling edge detection.
DMAC_B_EXTERNAL_DETECTION_RISING_EDGE	Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_FALLING_RISING_EDGE	Falling/Rising edge detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.
DMAC_B_EXTERNAL_DETECTION_NO_DETECTION	Not using hardware detection.

fsp_acc_control_ip_t [3/3]

enum fsp_acc_control_ip_t

access control.

fsp_mst_acc_control_ip_t [2/2]

enum fsp_mst_acc_control_ip_t

master access control.

ioport_peripheral_t

enum ioport_peripheral_t

Superset of all peripheral functions.

Enumerator
IOPORT_PERIPHERAL_MODE0	Pin will function as a Mode0 peripheral pin
IOPORT_PERIPHERAL_MODE1	Pin will function as a Mode1 peripheral pin
IOPORT_PERIPHERAL_MODE2	Pin will function as a Mode2 peripheral pin
IOPORT_PERIPHERAL_MODE3	Pin will function as a Mode3 peripheral pin
IOPORT_PERIPHERAL_MODE4	Pin will function as a Mode4 peripheral pin
IOPORT_PERIPHERAL_MODE5	Pin will function as a Mode5 peripheral pin
IOPORT_PERIPHERAL_MODE6	Pin will function as a Mode6 peripheral pin
IOPORT_PERIPHERAL_MODE7	Pin will function as a Mode7 peripheral pin
IOPORT_PERIPHERAL_MODE8	Pin will function as a Mode8 peripheral pin
IOPORT_PERIPHERAL_MODE9	Pin will function as a Mode9 peripheral pin
IOPORT_PERIPHERAL_MODE10	Pin will function as a Mode10 peripheral pin
IOPORT_PERIPHERAL_MODE11	Pin will function as a Mode11 peripheral pin
IOPORT_PERIPHERAL_MODE12	Pin will function as a Mode12 peripheral pin
IOPORT_PERIPHERAL_MODE13	Pin will function as a Mode13 peripheral pin
IOPORT_PERIPHERAL_MODE14	Pin will function as a Mode14 peripheral pin
IOPORT_PERIPHERAL_MODE15	Pin will function as a Mode15 peripheral pin
IOPORT_PERIPHERAL_MODE1	Pin will function as a Mode1 peripheral pin
IOPORT_PERIPHERAL_MODE2	Pin will function as a Mode2 peripheral pin
IOPORT_PERIPHERAL_MODE3	Pin will function as a Mode3 peripheral pin
IOPORT_PERIPHERAL_MODE4	Pin will function as a Mode4 peripheral pin
IOPORT_PERIPHERAL_MODE5	Pin will function as a Mode5 peripheral pin
IOPORT_PERIPHERAL_MODE6	Pin will function as a Mode6 peripheral pin
IOPORT_PERIPHERAL_MODE7	Pin will function as a Mode7 peripheral pin
IOPORT_PERIPHERAL_MODE8	Pin will function as a Mode8 peripheral pin

transfer_event_t [4/4]

enum transfer_event_t

Events that can trigger a callback function.

Enumerator
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.
TRANSFER_EVENT_TRANSFER_END	Transfer has completed.
TRANSFER_EVENT_TRANSFER_ERROR	Transfer error has occurred.

transfer_mode_t [4/4]

enum transfer_mode_t

Transfer mode describes what will happen when a transfer request occurs.

Enumerator
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_REPEAT	Repeat mode is like normal mode, except that when the transfer length reaches 0, the pointer to the repeat area and the transfer length will be reset to their initial values. If DMAC is used, the transfer repeats only transfer_info_t::num_blocks times. After the transfer repeats transfer_info_t::num_blocks times, transfer requests will not cause any further transfers. If DTC is used, the transfer repeats continuously (no limit to the number of repeat transfers).
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_REPEAT_BLOCK	In addition to block mode features, repeat-block mode supports a ring buffer of blocks and offsets within a block (to split blocks into arrays of their first data, second data, etc.)
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.
TRANSFER_MODE_NORMAL	In normal mode, each transfer request causes a transfer of transfer_size_t from the source pointer to the destination pointer. The transfer length is decremented and the source and address pointers are updated according to transfer_addr_mode_t. After the transfer length reaches 0, transfer requests will not cause any further transfers. Normal mode.
TRANSFER_MODE_BLOCK	In block mode, each transfer request causes transfer_info_t::length transfers of transfer_size_t. After each individual transfer, the source and destination pointers are updated according to transfer_addr_mode_t. After the block transfer is complete, transfer_info_t::num_blocks is decremented. After the transfer_info_t::num_blocks reaches 0, transfer requests will not cause any further transfers. Block mode.

transfer_size_t [4/4]

enum transfer_size_t

Transfer size specifies the size of each individual transfer.

Enumerator
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.
TRANSFER_SIZE_1_BYTE	Each transfer transfers a 8-bit value.
TRANSFER_SIZE_2_BYTE	Each transfer transfers a 16-bit value.
TRANSFER_SIZE_4_BYTE	Each transfer transfers a 32-bit value.
TRANSFER_SIZE_8_BYTE	Each transfer transfers a 64-bit value.
TRANSFER_SIZE_16_BYTE	Each transfer transfers a 128-bit value.
TRANSFER_SIZE_32_BYTE	Each transfer transfers a 256-bit value.
TRANSFER_SIZE_64_BYTE	Each transfer transfers a 512-bit value.
TRANSFER_SIZE_128_BYTE	Each transfer transfers a 1024-bit value.

transfer_addr_mode_t [4/4]

enum transfer_addr_mode_t

Address mode specifies whether to modify (increment or decrement) pointer after each transfer.

Enumerator
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_OFFSET	Offset is added to the address pointer after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_DECREMENTED	Address pointer is decremented by associated transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.
TRANSFER_ADDR_MODE_INCREMENTED	Address pointer is incremented by associated transfer_size_t after each transfer. Address pointer is incremented by associated RZG::transfer_size_t after each transfer.
TRANSFER_ADDR_MODE_FIXED	Address pointer remains fixed after each transfer.

Function Documentation

SystemCoreClockUpdate()

void RZG::SystemCoreClockUpdate

(

void

)

Update SystemCoreClock variable based on current clock settings.

bsp_clock_init()

void RZG::bsp_clock_init

(

void

)

Initializes system clocks. Makes no assumptions about current register settings.

bsp_clock_freq_init_cfg()

void RZG::bsp_clock_freq_init_cfg

(

void

)

Clock frequency configuration. According to the information specified in the Clocks tab, the divider and clock selector are initialized.

bsp_prv_clock_selector_set()

void RZG::bsp_prv_clock_selector_set	(	fsp_priv_clock_selector_t	selector,
		uint32_t	clock_sel
	)

Set the Mux Control register to change the frequency.

Parameters

[in]	selector	Element number of the array that defines the clock selector.
[in]	clock_sel	Value to set in Mux Control register.

bsp_prv_clock_divider_set()

void RZG::bsp_prv_clock_divider_set	(	fsp_priv_clock_divider_t	divider,
		uint32_t	clock_div
	)

Set the Gear Control register to change the frequency.

Parameters

[in]	divider	Element number of the array that defines the clock divider.
[in]	clock_div	Value to set in Gear Control register.

bsp_irq_cfg()

void RZG::bsp_irq_cfg

(

void

)

Initialize interrupt controller.

Return values

None	In this device, this function does nothing. This function is written to share code with other devices.

Using the vector table information section that has been built by the linker and placed into ROM in the .vector_info. section, this function will initialize the ICU so that configured ELC events will trigger interrupts in the NVIC.

bsp_irq_cfg_s()

void RZG::bsp_irq_cfg_s

(

void

)

This function provides clock to DMA Controller (see section 'Precaution when use the peripheral modules which can initiate DMA Controller.' in the user's manual for detail) and enables IM33. It also enables any interrupt in a non-secure state.