Multi-Function Timer Pulse Unit 3 (r_mtu3)

Functions
fsp_err_t	R_MTU3_Open (timer_ctrl_t *const p_ctrl, timer_cfg_t const *const p_cfg)
fsp_err_t	R_MTU3_Stop (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Start (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_Reset (timer_ctrl_t *const p_ctrl)
fsp_err_t	R_MTU3_PeriodSet (timer_ctrl_t *const p_ctrl, mtu3_counter_t *const p_counter)
fsp_err_t	R_MTU3_InfoGet (timer_ctrl_t *const p_ctrl, mtu3_info_t *const p_info)
fsp_err_t	R_MTU3_StatusGet (timer_ctrl_t *const p_ctrl, mtu3_status_t *const p_status)
fsp_err_t	R_MTU3_CounterSet (timer_ctrl_t *const p_ctrl, uint32_t counter)
fsp_err_t	R_MTU3_OutputEnable (timer_ctrl_t *const p_ctrl, mtu3_output_pin_t pin_level)
fsp_err_t	R_MTU3_OutputDisable (timer_ctrl_t *const p_ctrl, mtu3_io_pin_t pin)
fsp_err_t	R_MTU3_AdcTriggerSet (timer_ctrl_t *const p_ctrl, mtu3_adc_compare_match_t which_compare_match, uint16_t compare_match_value)
fsp_err_t	R_MTU3_CallbackSet (timer_ctrl_t *const p_ctrl, void(*p_callback)(timer_callback_args_t *), void const *const p_context, timer_callback_args_t *const p_callback_memory)
fsp_err_t	R_MTU3_Close (timer_ctrl_t *const p_ctrl)

Detailed Description

Driver for the MTU3 peripherals on RZ microprocessor. This module implements the Timer Interface.

Overview

The MTU3 module can be used to measure external input signals, generate a periodic interrupt, or output a periodic or PWM signal to a MTIOC pin.

This module supports the MTU3 peripherals are 16-bit timers. The 16-bit timers are all treated the same in this module from the API perspective.

Features

The MTU3 module has the following features:

• Supports periodic mode and PWM mode.
• Supports phase counting mode.
• Supports count source of ELC events.
• Supports debounce filter on MTIOC pins.
• Signal can be output to a pin.
• Configurable period (counts per timer cycle).
• Supports runtime reconfiguration of period.
• APIs are provided to start, stop, and reset the counter.
• APIs are provided to get the current period, source clock frequency, and count direction.
• APIs are provided to get the current timer status and counter value.
• Supports PWM waveform generation.
• Supports start an ADC scan at a compare match value and updating the compare match value.
• Supports setting the counter value while the timer is stopped.
• Supports enabling and disabling output pins.
• Supports skipping overflow / comparison match interrupts for specific channels

Selecting a Timer

RZ microprocessor have timer peripherals: the Multi-Function Timer Pulse Unit 3 (MTU3). When selecting between them, consider these factors:

	MTU3
Low Power Modes	The MTU3 can operate in sleep mode.
Available Channels	The number of MTU3 channels is device specific. All currently supported MCUs have at least 9 MTU3 channels.
Timer Resolution	All MCUs have at least one 16-bit MTU3 timer.
Clock Source	-Bus clock: PCLKH
	-Core clock: PCLKH

Configuration

Build Time Configurations for r_mtu3

The following build time configurations are defined in fsp_cfg/r_mtu3_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Pin Output Support	Disabled Enabled Enabled with Extra Features	Disabled	If selected code for outputting a waveform to a pin is included in the build.
UVW Support	Enabled Disabled	Disabled	If selected code for UVW is included in the build.
Multiplex Interrupt	Enabled Disabled	Disabled	Enable multiplex interrupt for a single driver.

Configurations for Timers > Timer , Multi-Function Timer Pulse Unit 3 (r_mtu3)

This module can be added to the Stacks tab via New Stack > Timers > Timer , Multi-Function Timer Pulse Unit 3 (r_mtu3).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_timer0	Module name.
General > Channel	Channel number must exist on this MCU	0	Specify the hardware channel.
General > Mode	Periodic PWM	Periodic	Mode selection. Periodic: Generates periodic interrupts or square waves. One-shot: Generate a single interrupt or a pulse wave. Note: One-shot mode is implemented in software. ISRs must be enabled for one-shot even if callback is unused. PWM: Generates basic PWM waveforms. Triangle-Wave Symmetric PWM: Generates symmetric PWM waveforms with duty cycle determined by compare match set during a crest interrupt and updated at the next trough. Triangle-Wave Asymmetric PWM: Generates asymmetric PWM waveforms with duty cycle determined by compare match set during a crest/trough interrupt and updated at the next trough/crest.
General > TGRA(Output Compare or Input Capture Value)	Value must be a valid non-negative integer with a maximum configurable value of 0xFFFF	0x0000	Capture/Compare match A value.
General > TGRB(Output Compare or Input Capture Value)	Value must be a valid non-negative integer with a maximum configurable value of 0xFFFF	0x0000	Capture/Compare match B value.
General > Time Prescaler	Refer to the RZT Configuration tool for available options.	PCLKH divided by 1 (common ch)	Select time prescaler.
General > Clock Edge	Rising Falling Both	Rising	Select clock edge.
General > Counter Clear Source	Disabled TGRA TGRB	Disabled	Select counter clear source.
Input > Phase Count > Bit Mode	16-bit 32-bit	16-bit	Select Bit Mode
Input > Phase Count > Counting Mode	Refer to the RZT Configuration tool for available options.	None	Select Counting Mode
Input > Phase Count > Clock Pin Select	MTCLKA, MTCLKB MTCLKC, MTCLKD	MTCLKA, MTCLKB	Select Clock pin Select
Noise Filter > External Clock > Enable	MTCLKA Enabled MTCLKB Enabled MTCLKC Enabled MTCLKD Enabled		Sets the noise filter for the external clock. Since it is a setting common to all channels, it may be overwritten by other Stacks settings.
Noise Filter > External Clock > Clock Select	PCLK divided by 1 PCLK divided by 2 PCLK divided by 8 PCLK divided by 32	PCLK divided by 1	Select noise filter clock.
Noise Filter > Input Capture > Enable	MTIOC(ch)A Enabled MTIOC(ch)B Enabled		Select whether to enable extra features on this channel.
Noise Filter > Input Capture > Clock Select	PCLK divided by 1 PCLK divided by 8 PCLK divided by 32 Clock source	PCLK divided by 1	Select noise filter clock.
Output > Initial Output A	Refer to the RZT Configuration tool for available options.	No Output	Select TGRA initial output.
Output > Initial Output B	Refer to the RZT Configuration tool for available options.	No Output	Select TGRB initial output.
Interrupts > Callback	Name must be a valid C symbol	NULL	A user callback function can be specified here. If this callback function is provided, it will be called from the interrupt service routine (ISR) each time the timer period elapses
Interrupts > Overflow/Crest Interrupt Priority	MCU Specific Options		Select the overflow interrupt priority. This is the crest interrupt for triangle-wave PWM.
Interrupts > Capture A Interrupt Priority	MCU Specific Options		Select the interrupt priority for capture A.
Interrupts > Capture B Interrupt Priority	MCU Specific Options		Select the interrupt priority for capture B.
Interrupts (GPT_SEL) > Callback	Name must be a valid C symbol	NULL	A user callback function can be specified here. If this callback function is provided, it will be called from the interrupt service routine (ISR) each time the timer period elapses
Interrupts (GPT_SEL) > Overflow/Crest Interrupt Source	MCU Specific Options		Select the overflow interrupt source. This is the crest interrupt for triangle-wave PWM.
Interrupts (GPT_SEL) > Capture A Interrupt Source	MCU Specific Options		Select the interrupt source for capture A.
Interrupts (GPT_SEL) > Capture B Interrupt Source	MCU Specific Options		Select the interrupt source for capture B.
Interrupts (GPT_SEL) > INT0 Interrupt Priority	MCU Specific Options		Select the interrupt priority for int0.
Interrupts (GPT_SEL) > INT1 Interrupt Priority	MCU Specific Options		Select the interrupt priority for int1.
Interrupts (GPT_SEL) > INT2 Interrupt Priority	MCU Specific Options		Select the interrupt priority for int2.
Interrupts (GPT_SEL) > INT3 Interrupt Priority	MCU Specific Options		Select the interrupt priority for int3.
Interrupts (GPT_SEL) > INT4 Interrupt Priority	MCU Specific Options		Select the interrupt priority for int4.
Extra Features > MTU5 > Interrupts > Capture U Interrupt Priority	MCU Specific Options		Select the interrupt priority for capture U.
Extra Features > MTU5 > Interrupts > Capture V Interrupt Priority	MCU Specific Options		Select the interrupt priority for capture V.
Extra Features > MTU5 > Interrupts > Capture W Interrupt Priority	MCU Specific Options		Select the interrupt priority for capture W.
Extra Features > MTU5 > Interrupts (GPT_SEL) > Capture U Interrupt Source	MCU Specific Options		Select the interrupt source for capture U.
Extra Features > MTU5 > Interrupts (GPT_SEL) > Capture V Interrupt Source	MCU Specific Options		Select the interrupt source for capture V.
Extra Features > MTU5 > Interrupts (GPT_SEL) > Capture W Interrupt Source	MCU Specific Options		Select the interrupt source for capture W.
Extra Features > MTU5 > U Count	Value must be a valid non-negative integer with a maximum configurable value of 0xFFFF	0x0000	Timer U Counter.
Extra Features > MTU5 > V Count	Value must be a valid non-negative integer with a maximum configurable value of 0xFFFF	0x0000	Timer V Counter.
Extra Features > MTU5 > W Count	Value must be a valid non-negative integer with a maximum configurable value of 0xFFFF	0x0000	Timer W Counter.
Extra Features > MTU5 > U Clock Select	Refer to the RZT Configuration tool for available options.	PCLKH divided by 1	Select U time prescaler.
Extra Features > MTU5 > V Clock Select	Refer to the RZT Configuration tool for available options.	PCLKH divided by 1	Select V time prescaler.
Extra Features > MTU5 > W Clock Select	Refer to the RZT Configuration tool for available options.	PCLKH divided by 1	Select W time prescaler.
Extra Features > MTU5 > U Input Capture	Refer to the RZT Configuration tool for available options.	No func	Select U output level.
Extra Features > MTU5 > V Input Capture	Refer to the RZT Configuration tool for available options.	No func	Select V output level.
Extra Features > MTU5 > W Input Capture	Refer to the RZT Configuration tool for available options.	No func	Select W output level.
Extra Features > MTU5 > UVW Noise Filter Enable	Disabled Enabled Only U Enabled Only V Enabled Only W Enabled U and V Enabled U and W Enabled V and W Enabled	Disabled	Enable UVW noise filter.
Extra Features > MTU5 > UVW Noise Filter Clock Select	PCLKH divided by 1 PCLKH divided by 8 PCLKH divided by 32 Clock source	PCLKH divided by 1	Select UVW noise filter clock.
Extra Features > Interrupt Skipping > Skip Mode A	Mode 1 Mode 2	Mode 1	Selects interrupt skipping function 1 or 2(TIMTRA).
Extra Features > Interrupt Skipping > Skip Mode B	Mode 1 Mode 2	Mode 1	Selects interrupt skipping function 1 or 2(TIMTRB).
Extra Features > Interrupt Skipping > TCIV4 Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TCIV4 interrupts to skip.
Extra Features > Interrupt Skipping > TCIV3 Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TCIV3 interrupts to skip.
Extra Features > Interrupt Skipping > TCIV7 Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TCIV7 interrupts to skip.
Extra Features > Interrupt Skipping > TGIA6 Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TGIA6 interrupts to skip.
Extra Features > Interrupt Skipping > TRG4AN/TRG4BN Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TRG4AN/TRG4BN interrupts to skip.
Extra Features > Interrupt Skipping > TRG7AN/TRG7BN Interrupt Skip Count	0 1 2 3 4 5 6 7	0	Select the number of TRG7AN/TRG7BN interrupts to skip.
Extra Features > ADC Trigger > ADC A Compare Match (Raw Counts)	Must be a valid non-negative integer with a maximum configurable value of 65535 (0xffff).	0x0000	Timer A/D Converter start request cycle A (MTU4 or MTU7).
Extra Features > ADC Trigger > ADC B Compare Match (Raw Counts)	Must be a valid non-negative integer with a maximum configurable value of 65535 (0xffff).	0x0000	Timer A/D Converter start request cycle B (MTU4 or MTU7).
Extra Features > ADC Trigger > MTUn.TGRA (n = 0 to 4, 6, 7) Input Capture/Compare Match	Enabled Disabled	Disabled	A/D Conversion Start by MTUn.TGRA (n = 0 to 4, 6, 7) Input Capture/Compare Match or at Trough of MTUm.TCNT (m = 4 or 7) in Complementary PWM Mode.
Extra Features > Extra Features	Enabled Disabled	Disabled	Select whether to enable extra features on this channel.
ELC > MTU0 > Trigger Source	MCU Specific Options		ELC source that will trigger MTU0
ELC > MTU0 > Operation Select	Disabled Count Start Count Restart Input Capture	Disabled	Select operation for MTU0
ELC > MTU3 > Trigger Source	MCU Specific Options		ELC source that will trigger MTU3
ELC > MTU3 > Operation Select	Disabled Count Start Count Restart Input Capture	Disabled	Select operation for MTU3
ELC > MTU4 > Trigger Source	MCU Specific Options		ELC source that will trigger MTU4
ELC > MTU4 > Operation Select	Disabled Count Start Count Restart Input Capture	Disabled	Select operation for MTU4

Clock Configuration

The MTU3 clock is based on the PCLKH frequency. You can set the PCLKH frequency using the Clocks tab of the RZ microprocessor Configuration editor.

Pin Configuration

This module can use MTIOCA and MTIOCB pins as output pins for periodic or PWM signals.

This module can use MTIOCA and MTIOCB as input pins to measure input signals.

Usage Notes

Updating Period and Duty Cycle

The period and duty cycle are updated after the next counter compare match after calling R_MTU3_PeriodSet().

Periodic Output

The MTIOC pin toggles twice each time the timer expires in periodic mode. This is achieved by defining a PWM wave at a 50 percent duty cycle so that the period of the resulting square wave (from rising edge to rising edge) matches the period of the MTU3 timer. Since the periodic output is actually a PWM output, the time at the stop level is one cycle shorter than the time opposite the stop level for odd period values.

PWM Output

For the PWM output signal, the signal level at the start of the cycle and at the end of the cycle can be selected arbitrarily.

Triggering ELC Events with MTU3

The MTU3 timer can trigger the start of other peripherals. The Event Link Controller (r_elc) guide provides a list of all available peripherals.

Interrupt Skipping

When an interrupt skipping source is selected a hardware counter will increment each time the selected event occurs. Each interrupt past the first (up to the specified skip count) will be suppressed.

Phase Counting Mode

Phase count mode is provides 16-bit or 32-bit channels used in phase counting applications. The ability to set the count value of the channel and the function to obtain the count value are possible. For this operation, configure “Phase Count” appropriately. Example of setting for phase counting mode 1 are shown below.

Configuration	Options
General > Channel	- 1
General > Mode	- Periodic
Input > Phase Count > Bit Mode	- 16 bit
Input > Phase Count > Counting Mode	- Mode 1
Count > Phase Count > Pin Clock Select	- MTCLKA, MTCLKB

Examples

MTU3 Basic Example

This is a basic example of minimal use of the MTU3 in an application.

void mtu3_basic_example (void)
{
    fsp_err_t err = FSP_SUCCESS;


    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);


    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);


    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);

}

MTU3 Callback Example

This is an example of a timer callback.

/* Example callback called when timer expires. */
void timer_callback (timer_callback_args_t * p_args)
{
    if (TIMER_EVENT_CYCLE_END == p_args->event)
    {
        /* Add application code to be called periodically here. */
    }
}

MTU3 Free Running Counter Example

To use the MTU3 as a free running counter, select periodic mode and set the the Period to 0xFFFF for a 16-bit timer.

void mtu3_counter_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);


    /* (Optional) Stop the timer. */
    (void) R_MTU3_Stop(&g_timer0_ctrl);



    /* Read the current counter value. Counter value is in status.counter. */
    mtu3_status_t status;
    (void) R_MTU3_StatusGet(&g_timer0_ctrl, &status);

}

MTU3 Period Update Example

This an example of updating the period.

#define MTU3_EXAMPLE_MICROSEC_PER_SEC           (1000000)
#define MTU3_EXAMPLE_DESIRED_PERIOD_MICROSEC    (200)

/* This example shows how to calculate a new period value at runtime. */
void mtu3_period_calculation_example (void)
{
    fsp_err_t      err = FSP_SUCCESS;
    mtu3_counter_t mtu3_count;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Start the timer. */
    (void) R_MTU3_Start(&g_timer0_ctrl);


    /* Get the source clock frequency (in Hz). There are 3 ways to do this in FSP:
     *  - If the PCLKH  frequency has not changed since reset, the source clock frequency is
     *    BSP_PRV_PCLKH_FREQ_200_MHZ >> mtu3_extended_cfg_t::mtu3_clk_div
     *  - Use the R_MTU3_InfoGet function (it accounts for the divider).
     *  - Calculate the current PCLKH frequency using R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKH) and right shift
     *    by mtu3_extended_cfg_t::mtu3_clk_div.
     *
     * This example uses the 3rd option (R_FSP_SystemClockHzGet).
     */
    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKH) >> g_timer0_cfg.source_div;

    /* Calculate the desired period based on the current clock. Note that this calculation could overflow if the
     * desired period is larger than UINT16_MAX / pclkd_freq_hz. A cast to uint64_t is used to prevent this. */
    mtu3_count.tgra_counts =
        (uint16_t) (((uint64_t) pclkd_freq_hz * MTU3_EXAMPLE_DESIRED_PERIOD_MICROSEC) / MTU3_EXAMPLE_MICROSEC_PER_SEC);
    mtu3_count.tgrb_counts = (mtu3_count.tgra_counts / 2U);

    /* Set the calculated period. */
    err = R_MTU3_PeriodSet(&g_timer0_ctrl, &mtu3_count);
    handle_error(err);

}

MTU3 phase count Basic Example

This is an example of using the MTU3 to operate phase counting mode.

void mtu3_phase_count_example (void)
{
    fsp_err_t err = FSP_SUCCESS;

    /* Initializes the module. */
    err = R_MTU3_Open(&g_timer0_ctrl, &g_timer0_cfg);

    /* Handle any errors. This function should be defined by the user. */
    handle_error(err);

    /* Start the timer. */
    err = R_MTU3_Start(&g_timer0_ctrl);
    handle_error(err);

    /* Get phase counting information. Counter value is in status.counter. */
    timer_status_t status;
    err = R_MTU3_StatusGet(&g_timer0_ctrl, &status);
    handle_error(err);
}

Data Structures
struct	mtu3_output_pin_t
struct	mtu3_status_t
struct	mtu3_elc_operation_t
struct	mtu3_counter_t
struct	mtu3_info_t
struct	mtu3_instance_ctrl_t
struct	mtu3_extended_pwm_cfg_t
struct	mtu3_extended_uvw_cfg_t
struct	mtu3_extended_cfg_t

Enumerations
enum	mtu3_io_pin_level_t
enum	mtu3_io_pin_level_uvw_t
enum	mtu3_clock_edge_t
enum	mtu3_div_t
enum	mtu3_div_uvw_t
enum	mtu3_tcnt_clear_t
enum	mtu3_io_pin_t
enum	mtu3_elc_operation_option_t
enum	mtu3_noise_filter_setting_t
enum	mtu3_noise_filter_mtclk_setting_t
enum	mtu3_noise_filter_setting_uvw_t
enum	mtu3_noise_filter_clock_t
enum	mtu3_noise_filter_external_clock_t
enum	mtu3_interrupt_skip_mode_t
enum	mtu3_interrupt_skip_count_t
enum	mtu3_adc_compare_match_t
enum	mtu3_phase_counting_mode_t
enum	mtu3_bit_mode_t
enum	mtu3_external_clock_t

---

Data Structure Documentation

mtu3_output_pin_t

struct mtu3_output_pin_t

Configurations for output pins.

Data Fields
mtu3_io_pin_level_t	output_pin_level_a	I/O Control A.
mtu3_io_pin_level_t	output_pin_level_b	I/O Control B.

mtu3_status_t

struct mtu3_status_t

Current timer status.

Data Fields
uint32_t	counter	Current counter value.
uint32_t	tgru_counter	Current counter value(TGRU)
uint32_t	tgrv_counter	Current counter value(TGRV)
uint32_t	tgrw_counter	Current counter value(TGRW)
timer_state_t	state	Current timer state (running or stopped)

mtu3_elc_operation_t

struct mtu3_elc_operation_t

MTU3 configuration for event link function

Data Fields
mtu3_elc_operation_option_t	mtu0_elc_operation	MTU0 operation select.
mtu3_elc_operation_option_t	mtu3_elc_operation	MTU3 operation select.
mtu3_elc_operation_option_t	mtu4_elc_operation	MTU4 operation select.

mtu3_counter_t

struct mtu3_counter_t

MTU3 set counter.

Data Fields
uint32_t	tgra_counts	Counter value(TGRA)
uint32_t	tgrb_counts	Counter value(TGRB)
uint32_t	tgru_counts	Counter value(TGRU)
uint32_t	tgrv_counts	Counter value(TGRV)
uint32_t	tgrw_counts	Counter value(TGRW)

mtu3_info_t

struct mtu3_info_t

MTU3 information structure to store various information for a timer resource

Data Fields
timer_direction_t	count_direction	Clock counting direction of the timer.
uint32_t	clock_frequency[3]	Clock frequency of the timer counter.(For ch5, use clock_frequency[0]-[2].)
mtu3_counter_t	count_param

mtu3_instance_ctrl_t

struct mtu3_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when timer_api_t::open is called.

Data Fields
uint32_t	open
	Whether or not channel is open.
const timer_cfg_t *	p_cfg
	Pointer to initial configurations.
void *	p_reg
	Base register for this channel.
R_MTU_Type *	p_reg_com
	Base register for this channel(common ch)
void *	p_reg_nf
	Base register for this channel(noise fileter)
uint32_t	channel_mask
	Channel bitmask.
void(*	p_callback )(timer_callback_args_t *)
	Pointer to callback.
timer_callback_args_t *	p_callback_memory
	Pointer to optional callback argument memory.
void const *	p_context
	Pointer to context to be passed into callback function.

mtu3_extended_pwm_cfg_t

struct mtu3_extended_pwm_cfg_t

MTU3 extension for advanced PWM features.

Data Fields
mtu3_interrupt_skip_mode_t	interrupt_skip_mode_a	Selects interrupt skipping function 1 or 2(TIMTRA)
mtu3_interrupt_skip_mode_t	interrupt_skip_mode_b	Selects interrupt skipping function 1 or 2(TIMTRB)
uint16_t	adc_a_compare_match	Timer A/D Converter Start Request Cycle A (MTU4 or MTU7)
uint16_t	adc_b_compare_match	Timer A/D Converter Start Request Cycle B (MTU4 or MTU7)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tciv4	TCIV4 Interrupt Skipping Count Setting(TITCR1A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgia3	TGIA3 Interrupt Skipping Count Setting(TITCR1A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tciv7	TCIV7 Interrupt Skipping Count Setting(TITCR1B)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgia6	TGIA6 Interrupt Skipping Count Setting(TITCR1B)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgr4an_bn	TRG4AN/TRG4BN Interrupt Skipping Count Setting(TITCR2A)
mtu3_interrupt_skip_count_t	interrupt_skip_count_tgr7an_bn	TRG7AN/TRG7BN Interrupt Skipping Count Setting(TITCR2B)

mtu3_extended_uvw_cfg_t

struct mtu3_extended_uvw_cfg_t

MTU3 extension for ch5.

Data Fields
uint16_t	tgru_val	Capture/Compare match U register.
uint16_t	tgrv_val	Capture/Compare match V register.
uint16_t	tgrw_val	Capture/Compare match W register.
mtu3_div_uvw_t	mtu3_clk_div_u	Time Prescaler Select U register.
mtu3_div_uvw_t	mtu3_clk_div_v	Time Prescaler Select V register.
mtu3_div_uvw_t	mtu3_clk_div_w	Time Prescaler Select W register.
mtu3_io_pin_level_uvw_t	output_pin_level_u	I/O Control U register.
mtu3_io_pin_level_uvw_t	output_pin_level_v	I/O Control V register.
mtu3_io_pin_level_uvw_t	output_pin_level_w	I/O Control W register.
mtu3_noise_filter_setting_uvw_t	noise_filter_mtioc_setting_uvw
mtu3_noise_filter_clock_t	noise_filter_mtioc_clk_uvw
uint8_t	capture_u_ipl	Capture/Compare match U interrupt priority.
uint8_t	capture_v_ipl	Capture/Compare match V interrupt priority.
uint8_t	capture_w_ipl	Capture/Compare match W interrupt priority.
IRQn_Type	capture_u_irq	Capture/Compare match U interrupt.
IRQn_Type	capture_v_irq	Capture/Compare match V interrupt.
IRQn_Type	capture_w_irq	Capture/Compare match W interrupt.

mtu3_extended_cfg_t

struct mtu3_extended_cfg_t

The MTU3 extension constitutes a unique feature of MTU3.

Data Fields
uint32_t	tgra_val	Capture/Compare match A register.
uint32_t	tgrb_val	Capture/Compare match B register.
uint32_t	tgrc_val	Capture/Compare match C register (Does not exist in MTU ch1-2)
uint32_t	tgrd_val	Capture/Compare match D register (Does not exist in MTU ch1-2)
mtu3_div_t	mtu3_clk_div	Time Prescaler Select.
mtu3_clock_edge_t	clk_edge	Clock Edge Select.
mtu3_tcnt_clear_t	mtu3_clear	Counter Clear Source Select.
mtu3_output_pin_t	mtioc_ctrl_setting	I/O Control A, B.
mtu3_noise_filter_setting_t	noise_filter_mtioc_setting
mtu3_noise_filter_clock_t	noise_filter_mtioc_clk
mtu3_noise_filter_mtclk_setting_t	noise_filter_mtclk_setting
mtu3_noise_filter_external_clock_t	noise_filter_mtclk_clk
bool	adc_request_enable	A/D Converter Start Request Enable(ch5 and ch8 are excluded)
mtu3_elc_operation_t	mtu3_elc_event_operation	MTU3 event link operation.
uint8_t	capture_a_ipl	Capture/Compare match A interrupt priority.
uint8_t	capture_b_ipl	Capture/Compare match B interrupt priority.
IRQn_Type	capture_a_irq	Capture/Compare match A interrupt.
IRQn_Type	capture_b_irq	Capture/Compare match B interrupt.
mtu3_extended_uvw_cfg_t const *	p_uvw_cfg	Advanced MTU ch5 features, optional.
mtu3_extended_pwm_cfg_t const *	p_pwm_cfg	Advanced PWM features, optional.
mtu3_phase_counting_mode_t	counting_mode	Select the counting mode.
mtu3_bit_mode_t	bit_mode	Select bit mode.
mtu3_external_clock_t	external_clock	Select External Clock Input Pins.
uint8_t	capture_a_source_select	Identify the GPT_INT for capture a.
uint8_t	capture_b_source_select	Identify the GPT_INT for capture b.
uint8_t	cycle_end_source_select	Identify the GPT_INT for capture overflow/underflow.

Enumeration Type Documentation

mtu3_io_pin_level_t

enum mtu3_io_pin_level_t

I/O Level Select

Enumerator
MTU3_IO_PIN_LEVEL_NO_OUTPUT	Output prohibited.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_LOW	Initial output is low. Low output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_HIGH	Initial output is low. High output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_LOW_COMPARE_TOGGLE	Initial output is low. Toggle output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_LOW	Initial output is high. Low output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_HIGH	Initial output is high. High output at compare match.
MTU3_IO_PIN_LEVEL_INITIAL_HIGH_COMPARE_TOGGLE	Initial output is high. Toggle output at compare match.
MTU3_IO_PIN_LEVEL_INPUT_RISING_EDGE	Input capture at rising edge.
MTU3_IO_PIN_LEVEL_INPUT_FALLING_EDGE	Input capture at falling edge.
MTU3_IO_PIN_LEVEL_INPUT_BOTH_EDGE	Input capture at both edge.
MTU3_IO_PIN_LEVEL_INPUT_A_MTU1_TCNT_CH0	Capture input source is the clock source for counting in MTU1. (ch0)
MTU3_IO_PIN_LEVEL_INPUT_A_MTU0_TGRA_COMPARE_CH1	Input capture at generation of MTU0.TGRA compare match/input capture. (ch1)
MTU3_IO_PIN_LEVEL_INPUT_B_MTU1_TCNT_CH0_8	Capture input source is the clock source for counting in MTU1. (ch0, 8)

mtu3_io_pin_level_uvw_t

enum mtu3_io_pin_level_uvw_t

I/O Level Select(MTU5)

Enumerator
MTU3_IO_PIN_LEVEL_UVW_NO_FUNC	No function.
MTU3_IO_PIN_LEVEL_UVW_INPUT_RISING_EDGE	Input capture at rising edge.
MTU3_IO_PIN_LEVEL_UVW_INPUT_FALLING_EDGE	Input capture at falling edge.
MTU3_IO_PIN_LEVEL_UVW_INPUT_BOTH_EDGE	Input capture at both edges.
MTU3_IO_PIN_LEVEL_UVW_INPUT_MTU8_TGRC_COMPARE	Input capture on generation of compare match with MTU8.TGRC.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_TROUGH	Measurement of low pulse width of external input signal.Capture at trough in complementary PWM mode.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_CREST	Measurement of low pulse width of external input signal.Capture at crest of complementary PWM mode.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_LOW_CREST_TROUGH	Measurement of low pulse width of external input signal.Capture at crest and trough of complementary PWM mode.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_TROUGH	Measurement of high pulse width of external input signal.Capture at trough in complementary PWM mode.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_CREST	Measurement of high pulse width of external input signal.Capture at crest of complementary PWM mode.
MTU3_IO_PIN_LEVEL_UVW_EXTERNAL_HIGH_CREST_TROUGH	Measurement of high pulse width of external input signal.Capture at crest and trough of complementary PWM mode.

mtu3_clock_edge_t

enum mtu3_clock_edge_t

Clock Edge Select

Enumerator
MTU3_CLOCK_EDGE_RISING	Count at rising edge.
MTU3_CLOCK_EDGE_FALLING	Count at falling edge.
MTU3_CLOCK_EDGE_BOTH	Count at both edges.

mtu3_div_t

enum mtu3_div_t

Time Prescaler Select

Enumerator
MTU3_DIV_PCLKH_1	PCLKH divided by 1 (common ch)
MTU3_DIV_PCLKH_4	PCLKH divided by 4 (common ch)
MTU3_DIV_PCLKH_16	PCLKH divided by 16 (common ch)
MTU3_DIV_PCLKH_64	PCLKH divided by 64 (common ch)
MTU3_DIV_PCLKH_2	PCLKH divided by 2 (common ch)
MTU3_DIV_PCLKH_8	PCLKH divided by 8 (common ch)
MTU3_DIV_PCLKH_32	PCLKH divided by 32 (common ch)
MTU3_DIV_MTCLKA_CH_0	External clock: counts on MTCLKA pin input (ch0)
MTU3_DIV_MTCLKB_CH_0	External clock: counts on MTCLKB pin input (ch0)
MTU3_DIV_MTCLKC_CH_0	External clock: counts on MTCLKC pin input (ch0)
MTU3_DIV_MTCLKD_CH_0	External clock: counts on MTCLKD pin input (ch0)
MTU3_DIV_PCLKH_256_CH_0	PCLKH divided by 256 (ch0)
MTU3_DIV_PCLKH_1024_CH_0	PCLKH divided by 1024 (ch0)
MTU3_DIV_MTIOC1A_CH_0	External clock: counts on MTIOC1A pin input (ch0)
MTU3_DIV_MTCLKA_CH_1	External clock: counts on MTCLKA pin input (ch1)
MTU3_DIV_MTCLKB_CH_1	External clock: counts on MTCLKB pin input (ch1)
MTU3_DIV_PCLKH_256_CH_1	PCLKH divided by 256 (ch1)
MTU3_DIV_TCNT_CH1	Overflow/underflow of MTU2.TCNT.
MTU3_DIV_PCLKH_1024_CH_1	PCLKH divided by 1024 (ch1)
MTU3_DIV_MTCLKA_CH_2	External clock: counts on MTCLKA pin input (ch2)
MTU3_DIV_MTCLKB_CH_2	External clock: counts on MTCLKB pin input (ch2)
MTU3_DIV_MTCLKC_CH_2	External clock: counts on MTCLKC pin input (ch2)
MTU3_DIV_PCLKH_1024_CH_2	PCLKH divided by 1024 (ch2)
MTU3_DIV_PCLKH_256_CH_2	PCLKH divided by 256 (ch2)
MTU3_DIV_PCLKH_256_CH_3_4_6_7_8	PCLKH divided by 256 (ch3-4, 6-8)
MTU3_DIV_PCLKH_1024_CH_3_4_6_7_8	PCLKH divided by 1024 (ch3-4, 6-8)
MTU3_DIV_MTCLKA_CH_3_4_6_7_8	External clock: counts on MTCLKA pin input (ch3-4, 6-8)
MTU3_DIV_MTCLKB_CH_3_4_6_7_8	External clock: counts on MTCLKB pin input (ch3-4, 6-8)

mtu3_div_uvw_t

enum mtu3_div_uvw_t

Time Prescaler Select(MTU5)

Enumerator
MTU3_DIV_UVW_PCLKH_1	PCLKH divided by 1.
MTU3_DIV_UVW_PCLKH_4	PCLKH divided by 4.
MTU3_DIV_UVW_PCLKH_16	PCLKH divided by 16.
MTU3_DIV_UVW_PCLKH_64	PCLKH divided by 64.
MTU3_DIV_UVW_PCLKH_2	PCLKH divided by 2.
MTU3_DIV_UVW_PCLKH_8	PCLKH divided by 8.
MTU3_DIV_UVW_PCLKH_32	PCLKH divided by 32.
MTU3_DIV_UVW_PCLKH_256	PCLKH divided by 256.
MTU3_DIV_UVW_PCLKH_1024	PCLKH divided by 1024.
MTU3_DIV_UVW_MTIOC1A_RISING_EDGE	External clock: Counts at the rising edge on MTIOC1A pin input.
MTU3_DIV_UVW_MTIOC1A_FALLING_EDGE	External clock: Counts at the falling edge on MTIOC1A pin input.
MTU3_DIV_UVW_MTIOC1A_BOTH_EDGE	External clock: Counts at the both edges on MTIOC1A pin input.

mtu3_tcnt_clear_t

enum mtu3_tcnt_clear_t

Counter Clear Source Select

Enumerator
MTU3_TCNT_CLEAR_DISABLE	TCNT clearing disabled.
MTU3_TCNT_CLEAR_TGRA	TCNT cleared by TGRA compare match/input capture.
MTU3_TCNT_CLEAR_TGRB	TCNT cleared by TGRB compare match/input capture.

mtu3_io_pin_t

enum mtu3_io_pin_t

Level of MTU3 pin

Enumerator
MTU3_IO_PIN_MTIOCA	MTIOCA.
MTU3_IO_PIN_MTIOCB	MTIOCB.
MTU3_IO_PIN_MTIOCA_AND_MTIOCB	MTIOCA and MTIOCB.

mtu3_elc_operation_option_t

enum mtu3_elc_operation_option_t

MTU3 event group operation

Note

Event link must be configured by the ELC

Enumerator
MTU3_EVENT_OPERATION_SELECT_COUNT_START	The MTU event operation is set to start counting.
MTU3_EVENT_OPERATION_SELECT_COUNT_RESTART	The MTU event operation is set to restart counting.
MTU3_EVENT_OPERATION_SELECT_INPUT_CAPTURE	The MTU event operation is set to input capture.
MTU3_EVENT_OPERATION_SELECT_DISABLE	The MTU event operation is set to disable.

mtu3_noise_filter_setting_t

enum mtu3_noise_filter_setting_t

Disables or enables the noise filter for input from the MTIOCnA pin

Enumerator
MTU3_NOISE_FILTER_DISABLE	The noise filter for the MTIOC pin is disabled.
MTU3_NOISE_FILTER_A_ENABLE	The noise filter for the MTIOCA pin is enabled.
MTU3_NOISE_FILTER_B_ENABLE	The noise filter for the MTIOCB pin is enabled.

mtu3_noise_filter_mtclk_setting_t

enum mtu3_noise_filter_mtclk_setting_t

Disables or enables the noise filter for the external clock input pins of the MTU

Enumerator
MTU3_NOISE_FILTER_EXTERNAL_DISABLE	The noise filter for the MTCLK pin is disabled.
MTU3_NOISE_FILTER_EXTERNAL_A_ENABLE	The noise filter for the MTCLKA pin is enabled.
MTU3_NOISE_FILTER_EXTERNAL_B_ENABLE	The noise filter for the MTCLKB pin is enabled.
MTU3_NOISE_FILTER_EXTERNAL_C_ENABLE	The noise filter for the MTCLKC pin is enabled.
MTU3_NOISE_FILTER_EXTERNAL_D_ENABLE	The noise filter for the MTCLKD pin is enabled.

mtu3_noise_filter_setting_uvw_t

enum mtu3_noise_filter_setting_uvw_t

Disables or enables the noise filter for input from the MTIC5U, MTIC5V, MTIC5W pin

Enumerator
MTU3_NOISE_FILTER_UVW_DISABLE	The noise filter for the MTIOC pin is disabled.
MTU3_NOISE_FILTER_UVW_U_ENABLE	The noise filter for the MTIC5U pin is enabled.
MTU3_NOISE_FILTER_UVW_V_ENABLE	The noise filter for the MTIC5V pin is enabled.
MTU3_NOISE_FILTER_UVW_W_ENABLE	The noise filter for the MTIC5W pin is enabled.

mtu3_noise_filter_clock_t

enum mtu3_noise_filter_clock_t

Enumerator
MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_1	PCLK/1 - fast sampling.
MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_8	PCLK/8.
MTU3_NOISE_FILTER_CLOCK_PCLKH_DIV_32	PCLK/32 - slow sampling.
MTU3_NOISE_FILTER_CLOCK_SOURCE	Clock source for counting.

mtu3_noise_filter_external_clock_t

enum mtu3_noise_filter_external_clock_t

Enumerator
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_1	PCLK/1 - fast sampling.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_2	PCLK/2.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_8	PCLK/8.
MTU3_NOISE_FILTER_EXTERNAL_CLOCK_PCLKH_DIV_32	PCLK/32 - slow sampling.

mtu3_interrupt_skip_mode_t

enum mtu3_interrupt_skip_mode_t

Interrupt Skipping Function Select

Enumerator
MTU3_INTERRUPT_SKIP_MODE_1	Setting the TITCR1A or TITCR1B register enables.
MTU3_INTERRUPT_SKIP_MODE_2	Setting the TITCR2A or TITCR2B register enables.

mtu3_interrupt_skip_count_t

enum mtu3_interrupt_skip_count_t

Number of interrupts to skip between events

Enumerator
MTU3_INTERRUPT_SKIP_COUNT_0	Do not skip interrupts.
MTU3_INTERRUPT_SKIP_COUNT_1	Skip one interrupt.
MTU3_INTERRUPT_SKIP_COUNT_2	Skip two interrupts.
MTU3_INTERRUPT_SKIP_COUNT_3	Skip three interrupts.
MTU3_INTERRUPT_SKIP_COUNT_4	Skip four interrupts.
MTU3_INTERRUPT_SKIP_COUNT_5	Skip five interrupts.
MTU3_INTERRUPT_SKIP_COUNT_6	Skip six interrupts.
MTU3_INTERRUPT_SKIP_COUNT_7	Skip seven interrupts.

mtu3_adc_compare_match_t

enum mtu3_adc_compare_match_t

Trigger options to start A/D conversion.

Enumerator
MTU3_ADC_COMPARE_MATCH_ADC_A	Set A/D conversion start request value for MTU3 A/D converter start request A.
MTU3_ADC_COMPARE_MATCH_ADC_B	Set A/D conversion start request value for MTU3 A/D converter start request B.

mtu3_phase_counting_mode_t

enum mtu3_phase_counting_mode_t

Enumerator
MTU3_PHASE_COUNTING_MODE_NONE	Disable Counting Mode.
MTU3_PHASE_COUNTING_MODE_1	Mode 1.
MTU3_PHASE_COUNTING_MODE_200	Mode 2 (00)
MTU3_PHASE_COUNTING_MODE_201	Mode 2 (01)
MTU3_PHASE_COUNTING_MODE_210	Mode 2 (1x)
MTU3_PHASE_COUNTING_MODE_300	Mode 3 (00)
MTU3_PHASE_COUNTING_MODE_301	Mode 3 (01)
MTU3_PHASE_COUNTING_MODE_310	Mode 3 (1x)
MTU3_PHASE_COUNTING_MODE_4	Mode 4.
MTU3_PHASE_COUNTING_MODE_50	Mode 5 (0x)
MTU3_PHASE_COUNTING_MODE_51	Mode 5 (10)

mtu3_bit_mode_t

enum mtu3_bit_mode_t

Enumerator
MTU3_BIT_MODE_NORMAL_16BIT	normal mode(16bit mode)
MTU3_BIT_MODE_NORMAL_32BIT	normal mode(32bit mode)

mtu3_external_clock_t

enum mtu3_external_clock_t

Enumerator
MTU3_EXTERNAL_CLOCK_MTCLKA_B	MTCLKA, MTCLKB.
MTU3_EXTERNAL_CLOCK_MTCLKC_D	MTCLKC, MTCLKD.

Function Documentation

R_MTU3_Open()

fsp_err_t R_MTU3_Open	(	timer_ctrl_t *const	p_ctrl,
		timer_cfg_t const *const	p_cfg
	)

Initializes the timer module and applies configurations.

The MTU3 implementation of the general timer can accept a mtu3_extended_cfg_t extension parameter.

Return values

FSP_SUCCESS	Initialization was successful and timer has started.
FSP_ERR_ASSERTION	A required input pointer is NULL.
FSP_ERR_ALREADY_OPEN	Module is already open.
FSP_ERR_INVALID_MODE	PWM is only supported if MTU3_CFG_OUTPUT_SUPPORT_ENABLE is 2.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel requested in the p_cfg parameter is not available on this device.

R_MTU3_Stop()

fsp_err_t R_MTU3_Stop

(

timer_ctrl_t *const

p_ctrl

)

Stops timer.

Return values

FSP_SUCCESS	Timer successfully stopped.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_Start()

fsp_err_t R_MTU3_Start

(

timer_ctrl_t *const

p_ctrl

)

Starts timer.

Return values

FSP_SUCCESS	Timer successfully started.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_Reset()

fsp_err_t R_MTU3_Reset

(

timer_ctrl_t *const

p_ctrl

)

Resets the counter value to 0.

Note

This function also updates to the new period if no counter overflow has occurred since the last call to R_MTU3_PeriodSet().

Return values

FSP_SUCCESS	Counter value written successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_PeriodSet()

fsp_err_t R_MTU3_PeriodSet	(	timer_ctrl_t *const	p_ctrl,
		mtu3_counter_t *const	p_counter
	)

Sets period value provided. If the timer is running, the period will be updated after the next compare match. If the timer is stopped, this function resets the counter and updates the period.

Return values

FSP_SUCCESS	Period value written successfully.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_InfoGet()

fsp_err_t R_MTU3_InfoGet	(	timer_ctrl_t *const	p_ctrl,
		mtu3_info_t *const	p_info
	)

Get timer information and store it in provided pointer p_info.

Return values

FSP_SUCCESS	TGRx, count direction, frequency, structure successfully.
FSP_ERR_ASSERTION	p_ctrl or p_info was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_StatusGet()

fsp_err_t R_MTU3_StatusGet	(	timer_ctrl_t *const	p_ctrl,
		mtu3_status_t *const	p_status
	)

Get current timer status and store it in provided pointer p_status.

Return values

FSP_SUCCESS	Current timer state and counter value set successfully.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_CounterSet()

fsp_err_t R_MTU3_CounterSet	(	timer_ctrl_t *const	p_ctrl,
		uint32_t	counter
	)

Set counter value.

Note

Do not call this API while the counter is counting. The counter value can only be updated while the counter is stopped.

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.
FSP_ERR_IN_USE	The timer is running. Stop the timer before calling this function.

R_MTU3_OutputEnable()

fsp_err_t R_MTU3_OutputEnable	(	timer_ctrl_t *const	p_ctrl,
		mtu3_output_pin_t	pin_level
	)

Enable output for MTIOCA and/or MTIOCB.

Return values

FSP_SUCCESS	Output is enabled.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_OutputDisable()

fsp_err_t R_MTU3_OutputDisable	(	timer_ctrl_t *const	p_ctrl,
		mtu3_io_pin_t	pin
	)

Disable output for MTIOCA and/or MTIOCB.

Return values

FSP_SUCCESS	Output is disabled.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_AdcTriggerSet()

fsp_err_t R_MTU3_AdcTriggerSet	(	timer_ctrl_t *const	p_ctrl,
		mtu3_adc_compare_match_t	which_compare_match,
		uint16_t	compare_match_value
	)

Set A/D converter start request compare match value.

Note

MTU ch4, ch7 only

Return values

FSP_SUCCESS	Counter value updated.
FSP_ERR_ASSERTION	p_ctrl or p_status was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.

R_MTU3_CallbackSet()

fsp_err_t R_MTU3_CallbackSet	(	timer_ctrl_t *const	p_ctrl,
		void(*)(timer_callback_args_t *)	p_callback,
		void const *const	p_context,
		timer_callback_args_t *const	p_callback_memory
	)

Updates the user callback with the option to provide memory for the callback argument structure.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

R_MTU3_Close()

fsp_err_t R_MTU3_Close

(

timer_ctrl_t *const

p_ctrl

)

Stops counter, disables output pins, and clears internal driver data.

Return values

FSP_SUCCESS	Successful close.
FSP_ERR_ASSERTION	p_ctrl was NULL.
FSP_ERR_NOT_OPEN	The instance is not opened.