Functions
fsp_err_t	R_XSPI_OSPI_Open (spi_flash_ctrl_t p_ctrl, spi_flash_cfg_t const const p_cfg)

fsp_err_t	R_XSPI_OSPI_Close (spi_flash_ctrl_t *p_ctrl)

fsp_err_t	R_XSPI_OSPI_DirectWrite (spi_flash_ctrl_t p_ctrl, uint8_t const const p_src, uint32_t const bytes, bool const read_after_write)

fsp_err_t	R_XSPI_OSPI_DirectRead (spi_flash_ctrl_t p_ctrl, uint8_t const p_dest, uint32_t const bytes)

fsp_err_t	R_XSPI_OSPI_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)

fsp_err_t	R_XSPI_OSPI_XipEnter (spi_flash_ctrl_t *p_ctrl)

fsp_err_t	R_XSPI_OSPI_XipExit (spi_flash_ctrl_t *p_ctrl)

fsp_err_t	R_XSPI_OSPI_Write (spi_flash_ctrl_t p_ctrl, uint8_t const const p_src, uint8_t *const p_dest, uint32_t byte_count)

fsp_err_t	R_XSPI_OSPI_Erase (spi_flash_ctrl_t p_ctrl, uint8_t const p_device_address, uint32_t byte_count)

fsp_err_t	R_XSPI_OSPI_StatusGet (spi_flash_ctrl_t p_ctrl, spi_flash_status_t const p_status)

fsp_err_t	R_XSPI_OSPI_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)

fsp_err_t	R_XSPI_OSPI_DirectTransfer (spi_flash_ctrl_t p_ctrl, spi_flash_direct_transfer_t const p_transfer, spi_flash_direct_transfer_dir_t direction)

fsp_err_t	R_XSPI_OSPI_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)

Detailed Description

Driver for the xSPI peripheral on RZ microprocessor. This module implements the SPI Flash Interface.

Overview

The OSPI peripheral interfaces with an external OctaFlash chip to perform data I/O Operations.

Features

The OSPI driver has the following key features:

Perform data I/O Operation in multiple modes
- 1S-1S-1S(SPI)
- 8D-8D-8D(OPI) (Supports only Dual Data Rate when using 8 pins)
Can be configured with OctaFlash device on either of the 2 units
Memory mapped read access to the OctaFlash
Programming the OctaFlash device using single continuous write
Erasing the OctaFlash device
Sending device specific commands and reading back responses
3 byte addressing for 1S-1S-1S(SPI)
4 byte addressing for 1S-1S-1S(SPI) and 8D-8D-8D(OPI)
Auto-calibration for 8D-8D-8D(OPI) mode
Configurable byte order in 8D-8D-8D(OPI) mode except for memory mapping read
Optional DMAC support for data transmission when used with xSPI_OSPI.

Note: 1. The available chip select lines may differ between devices. A full list of selectable chip select lines is available in the User's Manual for your device.; 2. When using serial flash memory without a hardware reset pin, if this LSI is reset after the serial flash protocol setting has been changed from 1S-1S-1S protocol to another protocol mode by the user program, the protocol mode of the boot program does not coincide with the protocol mode of the serial flash memory, which causes a boot error.; 3. If DMAC support is enabled, this driver uses 64 bytes of .noncache_buffer space.

Configuration

Build Time Configurations for r_xspi_ospi

The following build time configurations are defined in driver/r_xspi_ospi_cfg.h:

Configuration	Options	Default	Description
Custom Address Space > Unit0 > CS0 > Start Address	MCU Specific Options		Start address of xSPI Unit0 CS0 in memory mapping mode.
Custom Address Space > Unit0 > CS0 > End Address	Address should be within xspi unit0 external address space	0x600FFFFF	End address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit0 > CS1 > Start Address	Address should be within xspi unit0 external address space	0x64000000	Start address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit0 > CS1 > End Address	Address should be within xspi unit0 external address space	0x640FFFFF	End address of xSPI Unit0 CS1 in memory mapping mode.
Custom Address Space > Unit1 > CS0 > Start Address	MCU Specific Options		Start address of xSPI Unit1 CS0 in memory mapping mode.
Custom Address Space > Unit1 > CS0 > End Address	Address should be within xspi unit1 external address space	0x680FFFFF	End address of xSPI Unit1 CS0 in memory mapping mode.
Custom Address Space > Unit1 > CS1 > Start Address	Address should be within xspi unit1 external address space	0x6C000000	Start address of xSPI Unit1 CS1 in memory mapping mode.
Custom Address Space > Unit1 > CS1 > End Address	Address should be within xspi unit1 external address space	0x6C0FFFFF	End address of xSPI Unit1 CS1 in memory mapping mode.
Custom Address Space > Custom Address Space Enable	MCU Specific Options		When disabled, Custom Address Space is not applied and address space is set according to Flash Size. When enabled, Flash Size is disabled and Custom Address Space settings are applied.
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Unit 0 Prefetch Function	Enable Disable	Disable	Enable prefetch function on memory-mapped reads of xSPI Unit 0.
Unit 1 Prefetch Function	Enable Disable	Disable	Enable prefetch function on memory-mapped reads of xSPI Unit 1.
Unit 0 IO voltage	MCU Specific Options		Voltage setting of xSPI Unit0.
Unit 1 IO voltage	MCU Specific Options		Voltage setting of xSPI Unit1.
DMAC Support	Enable Disable	Disable	Enable DMAC support for the OSPI module.

Configurations for Storage > OSPI (r_xspi_ospi)

This module can be added to the Stacks tab via New Stack > Storage > OSPI (r_xspi_ospi).

Configuration	Options	Default	Description
General > Name	Name must be a valid C symbol	g_ospi0	Module name.
General > Unit	Unit should be 0 or 1	0	Specify the XSPI unit number.
General > Chip Select	Chip Select 0 Chip Select 1	Chip Select 0	Specify the OSPI chip select line to use.
General > Flash Size	1MB 2MB 4MB 8MB 16MB 32MB 64MB	64MB	Specify the OctaFlash size.
General > SPI Protocol	1S-1S-1S (SPI) 8D-8D-8D (Dual Data Rate OPI)	1S-1S-1S (SPI)	Select the initial SPI protocol. SPI protocol can be changed in R_XSPI_OSPI_SpiProtocolSet().
General > Address Bytes	3 4	4	Select the number of address bytes.
8D-8D-8D(OPI) Mode > Auto-Calibration > Data latching delay	Must be a valid non-negative integer	0x08	Set this to 0 to enable auto-calibration. 0x08 is the default value
8D-8D-8D(OPI) Mode > Auto-Calibration > Auto-Calibration Address	Must be a valid non-negative integer	0x00	Set the address of the read/write destination to be performed for auto-calibration.
8D-8D-8D(OPI) Mode > Command Definitions > Page Program Command	Manual Entry	0x12ED	The command to program a page in 8D-8D-8D(OPI) Mode.
8D-8D-8D(OPI) Mode > Command Definitions > Dual Read Command	Manual Entry	0xEE11	The command to read in 8D-8D-8D(OPI) Mode (8DTRD).
8D-8D-8D(OPI) Mode > Command Definitions > Write Enable Command	Manual Entry	0x06F9	The command to enable write in 8D-8D-8D(OPI) Mode.
8D-8D-8D(OPI) Mode > Command Definitions > Status Command	Manual Entry	0x05FA	The command to query the status of a write or erase command in 8D-8D-8D(OPI) Mode.
8D-8D-8D(OPI) Mode > Command Length Bytes	Must be an integer between 1 and 2	2	Command length in bytes
8D-8D-8D(OPI) Mode > Memory Read Dummy Cycles	Must be an integer between 0 and 31	10	Memory read dummy cycles
8D-8D-8D(OPI) Mode > Byte Order	Byte0, Byte1, Byte2, Byte3 Byte1, Byte0, Byte3, Byte2	Byte0, Byte1, Byte2, Byte3	Byte order on the external bus. Note: When accesses without API (with memory mapping), the byte order is limited to Byte0, Byte1, Byte2, Byte3.
1S-1S-1S (SPI) Mode > Command Definitions > Page Program Command	Manual Entry	0x12	The command to program a page in 1S-1S-1S (SPI) Mode.
1S-1S-1S (SPI) Mode > Command Definitions > Read Command	Manual Entry	0x13	The command to read in 1S-1S-1S (SPI) Mode.
1S-1S-1S (SPI) Mode > Command Definitions > Write Enable Command	Manual Entry	0x06	The command to enable write in 1S-1S-1S (SPI) Mode.
1S-1S-1S (SPI) Mode > Command Definitions > Status Command	Manual Entry	0x05	The command to query the status of a write or erase command in 1S-1S-1S (SPI) Mode.
Common Command Definitions > Sector Erase Command	Manual Entry	0x21DE	The command to erase a sector. Set Sector Erase Size to 0 if unused.
Common Command Definitions > Block Erase Command	Manual Entry	0xDC23	The command to erase a block. Set Block Erase Size to 0 if unused.
Common Command Definitions > Chip Erase Command	Manual Entry	0xC738	The command to erase the entire chip. Set Chip Erase Command to 0 if unused.
Common Command Definitions > Write Status Bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.
Common Command Definitions > Sector Erase Size	Must be an integer greater than or equal to 0	4096	The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported.
Common Command Definitions > Block Erase Size	Must be an integer greater than or equal to 0	65536	The block erase size. Set Block Erase Size to 0 if Block Erase is not supported.
Chip Select Timing Setting > Command Interval	Refer to the RZT Configuration tool for available options.	7 CYCLES	Define the CS minimum idle term.
Chip Select Timing Setting > Pull-up Timing	No Extension Extend 1 cycle	No Extension	Define the CS negating extension
Chip Select Timing Setting > Pull-down Timing	No Extension Extend 1 cycle	No Extension	Define the CS asserting extension

Clock Configuration

The XSPI_CLKn frequencies can be set on the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.

Pin Configuration

The following pins are available to connect to an external OSPI device:

XSPIn_CKP: OSPI clock output
XSPIn_DS: OSPI data strobe signal
XSPIn_CS0: OSPI device 0 select
XSPIn_CS1: OSPI device 1 select
XSPIn_IO0: Data 0 I/O
XSPIn_IO1: Data 1 I/O
XSPIn_IO2: Data 2 I/O
XSPIn_IO3: Data 3 I/O
XSPIn_IO4: Data 4 I/O
XSPIn_IO5: Data 5 I/O
XSPIn_IO6: Data 6 I/O
XSPIn_IO7: Data 7 I/O

Note: Data pins and Chip Select pins must be configured with IOPORT_CFG_DRIVE_HIGH.

Usage Notes

OSPI Memory Mapped Access

After R_XSPI_OSPI_Open() completes successfully, the OctaFlash device contents are mapped to address 0x60000000 (unit 0) or 0x68000000 (unit 1) based on the unit configured and can be read like on-chip flash. When not using the cache, access the OctaFlash device via the mirror space 0x40000000 (unit 0) or 0x48000000 (unit 1). Unit 0 and Unit 1 support 128 MB of address space.

The address map details for the external address space xSPI in RZ/T2M and RZ/T2L is as follows:

Address	Space
0x40000000 to 0x43FFFFFF	unit 0 CS0 mirror space
0x44000000 to 0x47FFFFFF	unit 0 CS1 mirror space
0x48000000 to 0x4BFFFFFF	unit 1 CS0 mirror space
0x4C000000 to 0x4FFFFFFF	unit 1 CS1 mirror space
0x60000000 to 0x63FFFFFF	unit 0 CS0
0x64000000 to 0x67FFFFFF	unit 0 CS1
0x68000000 to 0x6BFFFFFF	unit 1 CS0
0x6C000000 to 0x6FFFFFFF	unit 1 CS1

The address map for the external address space xSPI in RZ/T2ME is as follows:

Address	Space
0x40000000 to 0x47FFFFFF	unit 0 CS0 mirror space + unit 0 CS1 mirror space
0x48000000 to 0x4FFFFFFF	unit 1 CS0 mirror space + unit 1 CS1 mirror space
0x60000000 to 0x67FFFFFF	unit 0 CS0 + unit 0 CS1
0x68000000 to 0x6FFFFFFF	unit 1 CS0 + unit 1 CS1

The address map for the external address space xSPI in RZ/T2H is as follows:

Address	Space
0x40000000 to 0x4FFFFFFF	unit 0 CS0 + unit 0 CS1
0x50000000 to 0x5FFFFFFF	unit 1 CS0 + unit 1 CS1

Note: When Custom Address Space Enable configuration setting for RZ/T2ME and RZ/T2H is Enable, start address of CS1 space depends on the CS1 start address set in Custom Address Space configuration. When Disable, the start address of CS1 space is set so that each CS uses half of the address space.

Auto-calibration

Auto-calibration procedure is triggered automatically when the 'Data latching delay' field in the configurator properties is set to 0. The user application is responsible for setting the appropriate preamble pattern before calling R_XSPI_OSPI_Open() with 8D-8D-8D(OPI) mode or changing the SPI protocol to 8D-8D-8D(OPI) using R_XSPI_OSPI_SpiProtocolSet() API. The appropriate preamble pattern can be written to the desired address using the R_XSPI_OSPI_Write() API while in the 1S-1S-1S(SPI) mode. Ensure that the same address is passed through the configurator. If the OctaFlash chip is already in 8D-8D-8D(OPI) mode, the preamble pattern must be programmed using the debugger before calling R_XSPI_OSPI_Open().

Chip Select Latencies

Chip select latencies can be set through the configurator. The default settings support 1S-1S-1S(SPI) at minimum latency. In case the driver is opened in 1S-1S-1S(SPI) mode and will be switched to 8D-8D-8D(OPI) mode later using R_XSPI_OSPI_SpiProtocolSet(), please select latencies required for 8D-8D-8D(OPI) before calling R_XSPI_OSPI_Open().

OctaFlash Commands

Set the erase commands based on intended mode of operation (1S-1S-1S(SPI) or 8D-8D-8D(OPI)). These commands cannot be changed during run-time.
Read, Write and Status commands for both 1S-1S-1S(SPI) and 8D-8D-8D(OPI) are configured allowing switching between the modes at run-time.

OSPI Data and IAR

When using the IAR compiler, OSPI data must be const qualified to be downloaded by the debugger.

Limitations

When using the xSPI_OSPI driver, it is necessary to set the MPU with External address space xSPIn (0x60000000 - 0x6FFFFFFF) as the cacheable area and Mirror area of external address space xSPIn (0x40000000 - 0x4FFFFFFF) as the non-cacheable area.
Prefetch function support for memory-mapping access is applied to all slave devices connected xSPI0 or xSPI1. When connecting different types of devices (for example, QSPI and OSPI) to same xSPI unit, make sure that the prefetch function settings are the same.
When Enable is selected in the Custom Address Space Enable configuration, Custom Address Space settings are applied to all slave devices connected xSPI0 or xSPI1. When using different types of xSPI modules (for example, xSPI_QSPI and xSPI_OSPI), make sure that Custom Address Space configuration settings are the same for all xSPI modules.

Examples

Basic Example

This is a basic example of minimal use of the OSPI in an application. When using the section definition in the example below, the user must define it separately in the linker configuration file.

#define OSPI_EXAMPLE_DATA_LENGTH    (1024)
uint8_t g_dest[OSPI_EXAMPLE_DATA_LENGTH];
/* Place data in the .ospi_flash section to flash it during programming. */
const uint8_t g_src[OSPI_EXAMPLE_DATA_LENGTH] BSP_PLACE_IN_SECTION(".ospi_flash") = "ABCDEFGHIJKLMNOPQRSTUVWXYZ";
/* Place code in the .code_in_ospi section to flash it during programming. */
void r_ospi_example_function(void) BSP_PLACE_IN_SECTION(".code_in_ospi") __attribute__((noinline));
void r_ospi_example_function (void)
{
    /* Add code here. */
}
void r_ospi_basic_example (void)
{
    /* Open the OSPI instances */
    fsp_err_t err = R_XSPI_OSPI_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    handle_error(err);
    /* (Optional) Change 1S-1S-1S(SPI) to 8D-8D-8D(OPI) mode */
    r_ospi_example_spi_to_opi();
    /* After R_XSPI_OSPI_Open() and any required device specific initialization, data can be read directly from the OSPI flash. */
    memcpy(&g_dest[0], &g_src[0], OSPI_EXAMPLE_DATA_LENGTH);
    /* After R_XSPI_OSPI_Open() and any required device specific initialization, functions in the OSPI flash can be called. */
    r_ospi_example_function();
}

Reading Status Register Example (R_XSPI_OSPI_DirectTransfer)

This is an example of using R_XSPI_OSPI_DirectTransfer with write direction followed by R_XSPI_OSPI_DirectTransfer with read direction to send the write enable command and read back the status register from the device.

#define OSPI_COMMAND_WRITE_ENABLE            (0x06U)
#define OSPI_COMMAND_READ_STATUS_REGISTER    (0x05U)
void r_ospi_direct_example (void)
{
    spi_flash_direct_transfer_t ospi_test_direct_transfer =
    {
        .command        = OSPI_COMMAND_WRITE_ENABLE,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 0U,
        .data_length    = 0U,
        .dummy_cycles   = 0U
    };
    /* Open the OSPI instance. */
    fsp_err_t err = R_XSPI_OSPI_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    handle_error(err);
    /* Write Enable */
    err = R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);
    /* Read Status Register */
    ospi_test_direct_transfer.command     = OSPI_COMMAND_READ_STATUS_REGISTER;
    ospi_test_direct_transfer.data_length = 1U;
    err = R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);
    /* Check if Write Enable is set */
    if (OSPI_WEN_BIT_MASK != (ospi_test_direct_transfer.data & OSPI_WEN_BIT_MASK))
    {
        __BKPT(0);
    }
}

Protocol Set Example (R_XSPI_OSPI_SpiProtocolSet)

This is an example of using R_XSPI_OSPI_SpiProtocolSet to change the operating mode from 1S-1S-1S(SPI) to 8D-8D-8D(OPI) and the specific configuration procedure for OctaFlash.

static void r_ospi_example_spi_to_opi (void)
{
    r_ospi_write_enable_and_verify();
    spi_flash_direct_transfer_t ospi_test_direct_transfer =
    {
        .command        = OSPI_COMMAND_WCR2_SPI_MODE,
        .address        = 0U,
        .data           = 0U,
        .command_length = 1U,
        .address_length = 4U,
        .data_length    = 1U,
        .dummy_cycles   = 0U
    };
    /* Change dummy cycles according to requested frequency, consider 100MHz for this example */
    ospi_test_direct_transfer.address = OSPI_CR2_ADDRESS_HEX_300;
    ospi_test_direct_transfer.data    = 0x5U; /* Sets 10 dummy cycles */
    fsp_err_t err =
        R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);
    /* Read CR2 and check if dummy cycles are updated */
    ospi_test_direct_transfer.command = OSPI_COMMAND_RCR2_SPI_MODE;
    err = R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);
    if (0x5 != ospi_test_direct_transfer.data)
    {
        __BKPT(0);
    }
    r_ospi_write_enable_and_verify();
    /* The OctaFlash chip is in 1S-1S-1S(SPI) mode. Change 8D-8D-8D(OPI) mode */
    ospi_test_direct_transfer.command = OSPI_COMMAND_WCR2_SPI_MODE;
    ospi_test_direct_transfer.address = 0x0U;
    ospi_test_direct_transfer.data    = OSPI_CR2_OPI_SETTING;
    err = R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    handle_error(err);
    /* Change XSPI_CLK0 appropriately. For this example set XSPI_CLK0 = 100 MHz */
    ospi_example_change_omclk();
    /* Transition the OSPI peripheral to 8D-8D-8D(OPI) mode. */
    err = R_XSPI_OSPI_SpiProtocolSet(&g_ospi0_ctrl, SPI_FLASH_PROTOCOL_8D_8D_8D);
    handle_error(err);
    /* Verify that the chip is in requested 8D-8D-8D(OPI) mode */
    ospi_test_direct_transfer.command = OSPI_COMMAND_RCR2_SPI_MODE;
    err = R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    handle_error(err);
    if (OSPI_CR2_OPI_SETTING != ospi_test_direct_transfer.data)
    {
        __BKPT(0);
    }
}

Auto-calibration Example (R_XSPI_OSPI_Open, R_XSPI_OSPI_Write, R_XSPI_OSPI_SpiProtocolSet)

This is an example of using R_XSPI_OSPI_SpiProtocolSet to change the operating mode from 1S-1S-1S(SPI) to 8D-8D-8D(OPI) and allow the driver to initiate auto-calibration.

#define OSPI_OPI_PREAMBLE_PATTERN_LENGTH_BYTES    (16U)
#define OSPI_EXAMPLE_PREAMBLE_ADDRESS             (0x60000000U) /* Device connected to xSPI0_CS0 */
const uint8_t g_preamble_bytes[OSPI_OPI_PREAMBLE_PATTERN_LENGTH_BYTES] =
{
    0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x08, 0x00, 0x00, 0xF7, 0xFF, 0x00, 0x08, 0xF7, 0x00, 0xF7
};
void ospi_example_wait_until_wip (void)
{
    fsp_err_t          err = FSP_SUCCESS;
    spi_flash_status_t status;
    status.write_in_progress = true;
    uint32_t timeout = UINT32_MAX;
    while ((status.write_in_progress) && (--timeout))
    {
        err = R_XSPI_OSPI_StatusGet(&g_ospi0_ctrl, &status);
        handle_error(err);
    }
    if (0 == timeout)
    {
        handle_error(err);
    }
}
void r_ospi_auto_calibrate_example (void)
{
    /* Open the OSPI instance. */
    /* Set data_latch_delay_clocks to 0x0 to enable auto-calibration */
    fsp_err_t err = R_XSPI_OSPI_Open(&g_ospi0_ctrl, &g_ospi0_cfg);
    handle_error(err);
    uint8_t * preamble_pattern_addr = (uint8_t *) OSPI_EXAMPLE_PREAMBLE_ADDRESS;
    err = R_XSPI_OSPI_Write(&g_ospi0_ctrl,
                            g_preamble_bytes,
                            preamble_pattern_addr,
                            OSPI_OPI_PREAMBLE_PATTERN_LENGTH_BYTES);
    handle_error(err);
    /* Wait until write has been completed */
    ospi_example_wait_until_wip();
    /* Change from 1S-1S-1S(SPI) to 8D-8D-8D(OPI) mode */
    r_ospi_example_spi_to_opi();
}

Octaclk Update Example

This is an example of using R_CGC_SystemClockSet to change the Octal-SPI clock frequency during run time. The xSPI_CLK frequency must be updated before calling the R_XSPI_OSPI_SpiProtocolSet with appropriate clock source and divider settings required to be set for the new SPI protocol mode. Ensure that the clock source selected is started.

cgc_instance_ctrl_t g_cgc0_ctrl;
const cgc_cfg_t     g_cgc0_cfg = {NULL};
static void ospi_example_change_omclk (void)
{
    (void) R_CGC_Open(&g_cgc0_ctrl, &g_cgc0_cfg);
    /* Get system clock configuration */
    cgc_divider_cfg_t divider_cfg;
    cgc_clock_t       clock;
    R_CGC_SystemClockGet(&g_cgc0_ctrl, &clock, &divider_cfg);
    /* Update XSPI_CLK0 clock to 100.0MHz */
    divider_cfg.sckcr_b.fselxspi0   = CGC_FSEL_XSPI_CLOCK_DIV_8;
    divider_cfg.sckcr_b.divselxspi0 = CGC_DIVSEL_XSPI_CLOCK_DIV_3;
    R_CGC_SystemClockSet(&g_cgc0_ctrl, clock, &divider_cfg);
}

Direct Transfer Memory Write Example (R_XSPI_OSPI_DirectTransfer)

This is an example of using R_XSPI_OSPI_DirectTransfer() to write a page of data to memory space. If two memories are connected on the same unit's xSPI bus, memory mapping write may not be possible due to bus collisions caused by simultaneous accesses to the xSPI area. In this case, it is recommended to write data using R_XSPI_OSPI_DirectTransfer() instead of R_XSPI_OSPI_Write().

#define DIRECT_TRANSFER_MAX_DATA_BYTES    (8U)
void r_ospi_example_write_page_with_direct_transfer (void)
{
    spi_flash_direct_transfer_t ospi_test_direct_transfer =
    {
        .command        = OSPI_COMMAND_PAGE_PROGRAM,
        .address        = 0U,
        .data_u64       = 0U,
        .command_length = 1U,
        .address_length = 4U,
        .data_length    = DIRECT_TRANSFER_MAX_DATA_BYTES,
        .dummy_cycles   = 0U
    };
    /* Prepare a page of write data. */
    uint8_t write_data[OSPI_FLASH_PAGE_BYTES];
    for (uint32_t bytes = 0; bytes < OSPI_FLASH_PAGE_BYTES; bytes++)
    {
        write_data[bytes] = (uint8_t) bytes;
    }
    /* Repeat R_XSPI_OSPI_DirectTransfer until a page of data is written. */
    for (uint32_t trans = 0; trans < OSPI_FLASH_PAGE_BYTES / DIRECT_TRANSFER_MAX_DATA_BYTES; trans++)
    {
        /* Write Enable */
        r_ospi_write_enable_and_verify();
        /* Write memory with R_XSPI_OSPI_DirectTransfer */
        ospi_test_direct_transfer.data_u64 = *((uint64_t *) &write_data[trans * DIRECT_TRANSFER_MAX_DATA_BYTES]);
        ospi_test_direct_transfer.address  = OSPI_EXAMPLE_DESTINATION_CHIP_ADDRESS + trans *
                                             DIRECT_TRANSFER_MAX_DATA_BYTES;
        fsp_err_t err =
            R_XSPI_OSPI_DirectTransfer(&g_ospi0_ctrl, &ospi_test_direct_transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
        handle_error(err);
        /* Wait until write has been completed */
        ospi_example_wait_until_wip();
    }
}

Data Structures
struct	xspi_ospi_instance_ctrl_t

Enumerations
enum	xspi_ospi_chip_select_t

enum	xspi_ospi_memory_size_t

enum	xspi_ospi_command_interval_clocks_t

enum	xspi_ospi_cs_pullup_clocks_t

enum	xspi_ospi_cs_pulldown_clocks_t

enum	xspi_ospi_prefetch_function_t

enum	xspi_ospi_io_voltage_t

enum	xspi_ospi_byte_order_t

Data Structure Documentation

◆ xspi_ospi_instance_ctrl_t

struct xspi_ospi_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Enumeration Type Documentation

◆ xspi_ospi_chip_select_t

enum xspi_ospi_chip_select_t

Enumerator
XSPI_OSPI_CHIP_SELECT_0	Device connected to Chip-Select 0.
XSPI_OSPI_CHIP_SELECT_1	Device connected to Chip-Select 1.

◆ xspi_ospi_memory_size_t

enum xspi_ospi_memory_size_t

Enumerator
XSPI_OSPI_MEMORY_SIZE_1MB	Memory size 1MB.
XSPI_OSPI_MEMORY_SIZE_2MB	Memory size 2MB.
XSPI_OSPI_MEMORY_SIZE_4MB	Memory size 4MB.
XSPI_OSPI_MEMORY_SIZE_8MB	Memory size 8MB.
XSPI_OSPI_MEMORY_SIZE_16MB	Memory size 16MB.
XSPI_OSPI_MEMORY_SIZE_32MB	Memory size 32MB.
XSPI_OSPI_MEMORY_SIZE_64MB	Memory size 64MB.

◆ xspi_ospi_command_interval_clocks_t

enum xspi_ospi_command_interval_clocks_t

Enumerator
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_1	1 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_2	2 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_3	3 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_4	4 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_5	5 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_6	6 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_7	7 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_8	8 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_9	9 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_10	10 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_11	11 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_12	12 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_13	13 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_14	14 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_15	15 interval clocks
XSPI_OSPI_COMMAND_INTERVAL_CLOCKS_16	16 interval clocks

◆ xspi_ospi_cs_pullup_clocks_t

enum xspi_ospi_cs_pullup_clocks_t

Enumerator
XSPI_OSPI_CS_PULLUP_CLOCKS_NO_EXTENSION	CS asserting No extension.
XSPI_OSPI_CS_PULLUP_CLOCKS_1	CS asserting Extend 1 cycle.

◆ xspi_ospi_cs_pulldown_clocks_t

enum xspi_ospi_cs_pulldown_clocks_t

Enumerator
XSPI_OSPI_CS_PULLDOWN_CLOCKS_NO_EXTENSION	CS negating No extension.
XSPI_OSPI_CS_PULLDOWN_CLOCKS_1	CS negating Extend 1 cycle.

◆ xspi_ospi_prefetch_function_t

enum xspi_ospi_prefetch_function_t

Enumerator
XSPI_OSPI_PREFETCH_FUNCTION_DISABLE	Prefetch function disable.
XSPI_OSPI_PREFETCH_FUNCTION_ENABLE	Prefetch function enable.

◆ xspi_ospi_io_voltage_t

enum xspi_ospi_io_voltage_t

Enumerator
XSPI_OSPI_IO_VOLTAGE_1_8V	IO voltage 1.8V.
XSPI_OSPI_IO_VOLTAGE_3_3V	IO voltage 3.3V.

◆ xspi_ospi_byte_order_t

enum xspi_ospi_byte_order_t

Enumerator
XSPI_OSPI_BYTE_ORDER_0123	8D-8D-8D(OPI) byte order byte 0, byte 1, byte 2, byte 3
XSPI_OSPI_BYTE_ORDER_1032	8D-8D-8D(OPI) byte order byte 1, byte 0, byte 3, byte 2

Function Documentation

◆ R_XSPI_OSPI_Open()

fsp_err_t R_XSPI_OSPI_Open	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory.

Implements spi_flash_api_t::open.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_ctrl.
FSP_ERR_CALIBRATE_FAILED	Failed to perform auto-calibrate.

◆ R_XSPI_OSPI_Close()

fsp_err_t R_XSPI_OSPI_Close ( spi_flash_ctrl_t * p_ctrl )

Close the OSPI driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

Note: If another chip select of the same unit is used by other drivers, the other chip select operation will also stop when this function is executed.

◆ R_XSPI_OSPI_DirectWrite()

fsp_err_t R_XSPI_OSPI_DirectWrite	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the OctaFlash. API not supported. Use R_XSPI_OSPI_DirectTransfer

Implements spi_flash_api_t::directWrite.

Return values

FSP_ERR_UNSUPPORTED API not supported by OSPI.

◆ R_XSPI_OSPI_DirectRead()

fsp_err_t R_XSPI_OSPI_DirectRead	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the OctaFlash. API not supported. Use R_XSPI_OSPI_DirectTransfer.

Implements spi_flash_api_t::directRead.

Return values

FSP_ERR_UNSUPPORTED API not supported by OSPI.

◆ R_XSPI_OSPI_SpiProtocolSet()

fsp_err_t R_XSPI_OSPI_SpiProtocolSet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_SUCCESS	SPI protocol updated on MPU peripheral.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_CALIBRATE_FAILED	Failed to perform auto-calibrate.

◆ R_XSPI_OSPI_XipEnter()

fsp_err_t R_XSPI_OSPI_XipEnter ( spi_flash_ctrl_t * p_ctrl )

Enters XIP (execute in place) mode.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_ERR_UNSUPPORTED API not supported by OSPI.

◆ R_XSPI_OSPI_XipExit()

fsp_err_t R_XSPI_OSPI_XipExit ( spi_flash_ctrl_t * p_ctrl )

Exits XIP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Return values

FSP_ERR_UNSUPPORTED API not supported by OSPI.

◆ R_XSPI_OSPI_Write()

fsp_err_t R_XSPI_OSPI_Write	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	Another Write/Erase transaction is in progress.

Note: In this API, data can be written up to 64 bytes at a time if DMAC support is enabled. Otherwise, the number of bytes that can be written at one time depends on the MCU : 64 bytes for RZ/T2M and RZ/T2L, 8 bytes for RZ/T2ME and RZ/T2H.; This API performs page program operations to the device. Writing across pages is not supported. Please set the write address and write size according to the page size of your device.; In 8D-8D-8D(OPI) mode, written data must be even bytes in size.

◆ R_XSPI_OSPI_Erase()

fsp_err_t R_XSPI_OSPI_Erase	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase size defined in spi_flash_cfg_t, or byte_count is set to 0.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.

◆ R_XSPI_OSPI_StatusGet()

fsp_err_t R_XSPI_OSPI_StatusGet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

◆ R_XSPI_OSPI_BankSet()

fsp_err_t R_XSPI_OSPI_BankSet	(	spi_flash_ctrl_t *	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access.

Implements spi_flash_api_t::bankSet.

Return values

FSP_ERR_UNSUPPORTED API not supported by OSPI.

◆ R_XSPI_OSPI_DirectTransfer()

fsp_err_t R_XSPI_OSPI_DirectTransfer	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the OctaFlash.

Implements spi_flash_api_t::directTransfer.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

◆ R_XSPI_OSPI_AutoCalibrate()

fsp_err_t R_XSPI_OSPI_AutoCalibrate ( spi_flash_ctrl_t * p_ctrl )

Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by XSPI_OSPI.

Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_ERR_UNSUPPORTED API not supported by XSPI_OSPI

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_xspi_ospi

Configurations for Storage > OSPI (r_xspi_ospi)

Clock Configuration

Pin Configuration

Usage Notes

OSPI Memory Mapped Access

Auto-calibration

Chip Select Latencies

OctaFlash Commands

OSPI Data and IAR

Limitations

Examples

Basic Example

Reading Status Register Example (R_XSPI_OSPI_DirectTransfer)

Protocol Set Example (R_XSPI_OSPI_SpiProtocolSet)

Auto-calibration Example (R_XSPI_OSPI_Open, R_XSPI_OSPI_Write, R_XSPI_OSPI_SpiProtocolSet)

Octaclk Update Example

Direct Transfer Memory Write Example (R_XSPI_OSPI_DirectTransfer)

Data Structures

Enumerations

Data Structure Documentation

◆ xspi_ospi_instance_ctrl_t

Enumeration Type Documentation

◆ xspi_ospi_chip_select_t

◆ xspi_ospi_memory_size_t

◆ xspi_ospi_command_interval_clocks_t

◆ xspi_ospi_cs_pullup_clocks_t

◆ xspi_ospi_cs_pulldown_clocks_t

◆ xspi_ospi_prefetch_function_t

◆ xspi_ospi_io_voltage_t

◆ xspi_ospi_byte_order_t

Function Documentation

◆ R_XSPI_OSPI_Open()

◆ R_XSPI_OSPI_Close()

◆ R_XSPI_OSPI_DirectWrite()

◆ R_XSPI_OSPI_DirectRead()

◆ R_XSPI_OSPI_SpiProtocolSet()

◆ R_XSPI_OSPI_XipEnter()

◆ R_XSPI_OSPI_XipExit()

◆ R_XSPI_OSPI_Write()

◆ R_XSPI_OSPI_Erase()

◆ R_XSPI_OSPI_StatusGet()

◆ R_XSPI_OSPI_BankSet()

◆ R_XSPI_OSPI_DirectTransfer()

◆ R_XSPI_OSPI_AutoCalibrate()