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RZT Flexible Software Package Documentation
Release v3.0.0
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Driver for the xSPI peripheral on RZ microprocessor. This module implements the SPI Flash Interface.
The OSPI peripheral interfaces with an external OctaFlash chip to perform data I/O Operations.
The OSPI driver has the following key features:
Configuration | Options | Default | Description |
---|---|---|---|
Memory Mapping Address Space > Unit 0 > Chip Select 0 > Start Address | Address should be the start address of xspi unit 0 external address space | 0x60000000 | Start address of xSPI Unit 0 Chip Select 0 in memory mapping mode. |
Memory Mapping Address Space > Unit 0 > Chip Select 0 > End Address | Address should be within xspi unit 0 external address space | 0x600FFFFF | End address of xSPI Unit 0 Chip Select 1 in memory mapping mode. |
Memory Mapping Address Space > Unit 0 > Chip Select 1 > Start Address | Address should be within xspi unit 0 external address space | 0x64000000 | Start address of xSPI Unit 0 Chip Select 1 in memory mapping mode. |
Memory Mapping Address Space > Unit 0 > Chip Select 1 > End Address | Address should be within xspi unit 0 external address space | 0x640FFFFF | End address of xSPI Unit 0 Chip Select 1 in memory mapping mode. |
Memory Mapping Address Space > Unit 1 > Chip Select 0 > Start Address | Address should be the start address of xspi unit 1 external address space | 0x68000000 | Start address of xSPI Unit 1 Chip Select 0 in memory mapping mode. |
Memory Mapping Address Space > Unit 1 > Chip Select 0 > End Address | Address should be within xspi unit 1 external address space | 0x680FFFFF | End address of xSPI Unit 1 Chip Select 0 in memory mapping mode. |
Memory Mapping Address Space > Unit 1 > Chip Select 1 > Start Address | Address should be within xspi unit 1 external address space | 0x6C000000 | Start address of xSPI Unit 1 Chip Select 1 in memory mapping mode. |
Memory Mapping Address Space > Unit 1 > Chip Select 1 > End Address | Address should be within xspi unit 1 external address space | 0x6C0FFFFF | End address of xSPI Unit 1 Chip Select 1 in memory mapping mode. |
Memory Mapping Address Space > Memory Mapping Address Space Configuration Support | MCU Specific Options | Support status of Memory Mapping Address Space setting on this MCU. If Not supported, the address space set in Memory Mapping Address Space is invalid. | |
Parameter Checking |
| Default (BSP) | If selected code for parameter checking is included in the build. |
Unit 0 Prefetch Function |
| Disable | Enable prefetch function on memory-mapped reads of xSPI Unit 0. |
Unit 1 Prefetch Function |
| Disable | Enable prefetch function on memory-mapped reads of xSPI Unit 1. |
Unit 0 IO voltage | MCU Specific Options | Voltage setting of xSPI Unit 0. | |
Unit 1 IO voltage | MCU Specific Options | Voltage setting of xSPI Unit 1. | |
DMAC Support |
| Disable | Enable DMAC support for the OSPI module. |
Configuration | Options | Default | Description |
---|---|---|---|
General > Name | Name must be a valid C symbol | g_ospi0 | Module name. |
General > Unit | Unit should be 0 or 1 | 0 | Specify the XSPI unit number. |
General > Chip Select |
| Chip Select 0 | Specify the OSPI chip select line to use. |
General > Flash Size | MCU Specific Options | Specify the OctaFlash size. | |
General > SPI Protocol |
| 1S-1S-1S (SPI) | Select the initial SPI protocol. SPI protocol can be changed in R_XSPI_OSPI_SpiProtocolSet(). |
General > Address Bytes |
| 4 | Select the number of address bytes. |
8D-8D-8D(OPI) Mode > Auto-Calibration > Data latching delay | Must be a valid non-negative integer | 0x08 | Set this to 0 to enable auto-calibration. 0x08 is the default value |
8D-8D-8D(OPI) Mode > Auto-Calibration > Auto-Calibration Address | Must be a valid non-negative integer | 0x00 | Set the address of the read/write destination to be performed for auto-calibration. |
8D-8D-8D(OPI) Mode > Command Definitions > Page Program Command | Manual Entry | 0x12ED | The command to program a page in 8D-8D-8D(OPI) Mode. |
8D-8D-8D(OPI) Mode > Command Definitions > Dual Read Command | Manual Entry | 0xEE11 | The command to read in 8D-8D-8D(OPI) Mode (8DTRD). |
8D-8D-8D(OPI) Mode > Command Definitions > Write Enable Command | Manual Entry | 0x06F9 | The command to enable write in 8D-8D-8D(OPI) Mode. |
8D-8D-8D(OPI) Mode > Command Definitions > Status Command | Manual Entry | 0x05FA | The command to query the status of a write or erase command in 8D-8D-8D(OPI) Mode. |
8D-8D-8D(OPI) Mode > Command Length Bytes | Must be an integer between 1 and 2 | 2 | Command length in bytes |
8D-8D-8D(OPI) Mode > Memory Read Dummy Cycles | Must be an integer between 0 and 31 | 10 | Memory read dummy cycles |
8D-8D-8D(OPI) Mode > Byte Order |
| Byte0, Byte1, Byte2, Byte3 | Byte order on the external bus. Note: When accesses without API (with memory mapping), the byte order is limited to Byte0, Byte1, Byte2, Byte3. |
1S-1S-1S (SPI) Mode > Command Definitions > Page Program Command | Manual Entry | 0x12 | The command to program a page in 1S-1S-1S (SPI) Mode. |
1S-1S-1S (SPI) Mode > Command Definitions > Read Command | Manual Entry | 0x13 | The command to read in 1S-1S-1S (SPI) Mode. |
1S-1S-1S (SPI) Mode > Command Definitions > Write Enable Command | Manual Entry | 0x06 | The command to enable write in 1S-1S-1S (SPI) Mode. |
1S-1S-1S (SPI) Mode > Command Definitions > Status Command | Manual Entry | 0x05 | The command to query the status of a write or erase command in 1S-1S-1S (SPI) Mode. |
Common Command Definitions > Sector Erase Command | Manual Entry | 0x21DE | The command to erase a sector. Set Sector Erase Size to 0 if unused. |
Common Command Definitions > Block Erase Command | Manual Entry | 0xDC23 | The command to erase a block. Set Block Erase Size to 0 if unused. |
Common Command Definitions > Chip Erase Command | Manual Entry | 0xC738 | The command to erase the entire chip. Set Chip Erase Command to 0 if unused. |
Common Command Definitions > Write Status Bit | Must be an integer between 0 and 7 | 0 | Which bit contains the write in progress status returned from the Write Status Command. |
Common Command Definitions > Write Enable Bit | Must be an integer between 0 and 7 | 1 | Which bit contains the write enable status returned from the Write Status Command. |
Common Command Definitions > Sector Erase Size | Must be an integer greater than or equal to 0 | 4096 | The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported. |
Common Command Definitions > Block Erase Size | Must be an integer greater than or equal to 0 | 65536 | The block erase size. Set Block Erase Size to 0 if Block Erase is not supported. |
Chip Select Timing Setting > Command Interval | Refer to the RZT Configuration tool for available options. | 7 CYCLES | Define the CS minimum idle term. |
Chip Select Timing Setting > Pull-up Timing |
| No Extension | Define the CS negating extension |
Chip Select Timing Setting > Pull-down Timing |
| No Extension | Define the CS asserting extension |
The XSPI_CLKn frequencies can be set on the Clocks tab of the FSP Configuration editor or by using the CGC Interface at run-time.
The following pins are available to connect to an external OSPI device:
After R_XSPI_OSPI_Open() completes successfully, the OctaFlash device contents are mapped to External Address Space xSPIn or their mirror spaces and can be read like on-chip flash. Please refer to xSPI "Overview" section in your device's manual on address map details.
In the configurator properties, 'Memory Mapping Address Space Configuration Support' is set to either 'Supported' or 'Not Supported' depending on your device. The method of memory mapped access address configuration depends on the value of 'Memory Mapping Address Space Configuration Support'.
If 'Memory Mapping Address Space Configuration Support' is 'Supported', 'Memory Mapping Address Space' should be set appropriately for your device. The table below shows an example of 'Memory Mapping Address Space' configurations when 64MB flash is used as a slave device in each Chip Select.
Properties | RZ/T2ME | RZ/T2H |
---|---|---|
Memory Mapping Address Space > Unit 0 > Chip Select 0 > Start Address | 0x60000000 (Fixed) | 0x40000000 (Fixed) |
Memory Mapping Address Space > Unit 0 > Chip Select 0 > End Address | 0x63FFFFFF | 0x43FFFFFF |
Memory Mapping Address Space > Unit 0 > Chip Select 1 > Start Address | 0x64000000 | 0x48000000 |
Memory Mapping Address Space > Unit 0 > Chip Select 1 > End Address | 0x67FFFFFF | 0x4BFFFFFF |
Memory Mapping Address Space > Unit 1 > Chip Select 0 > Start Address | 0x68000000 (Fixed) | 0x50000000 (Fixed) |
Memory Mapping Address Space > Unit 1 > Chip Select 0 > End Address | 0x6BFFFFFF | 0x53FFFFFF |
Memory Mapping Address Space > Unit 1 > Chip Select 1 > Start Address | 0x6C000000 | 0x58000000 |
Memory Mapping Address Space > Unit 1 > Chip Select 1 > End Address | 0x6FFFFFFF | 0x5BFFFFFF |
Memory Mapping Address Space > Memory Mapping Address Space Configuration Support | Supported | Supported |
The address space of each chip select set by the above configuration is as follows.
Address Space of Each Chip Select | RZ/T2ME | RZ/T2H |
---|---|---|
Unit 0 Chip Select 0 Start Address | 0x60000000 (Fixed) | 0x40000000 (Fixed) |
Unit 0 Chip Select 0 End Address | 0x63FFFFFF | 0x43FFFFFF |
Unit 0 Chip Select 1 Start Address | 0x64000000 | 0x48000000 |
Unit 0 Chip Select 1 End Address | 0x67FFFFFF | 0x4BFFFFFF |
Unit 1 Chip Select 0 Start Address | 0x68000000 (Fixed) | 0x50000000 (Fixed) |
Unit 1 Chip Select 0 End Address | 0x6BFFFFFF | 0x53FFFFFF |
Unit 1 Chip Select 1 Start Address | 0x6C000000 | 0x58000000 |
Unit 1 Chip Select 1 End Address | 0x6FFFFFFF | 0x5BFFFFFF |
If 'Memory Mapping Address Space Configuration Support' is 'Not Supported' for your device, 'Memory Mapping Address Space' configurations are invalid. In this case, the start address of each chip select is fixed by device, and only the size of the address space is configured in 'Flash Size' property. The table below shows an example of the address space configuration when 64MB flash is used as a slave device in Unit 0 Chip Select 0.
Properties | RZ/T2M | RZ/T2L |
---|---|---|
Memory Mapping Address Space > Memory Mapping Address Space Configuration Support | Not Supported | Not Supported |
General > Unit | 0 | 0 |
General > Chip Select | 0 | 0 |
General > Flash Size | 64MB | 64MB |
The address space of each chip select set by the above configuration is as follows.
Address Space of Each Chip Select | RZ/T2M | RZ/T2L |
---|---|---|
Unit 0 Chip Select 0 Start Address | 0x60000000 (Fixed) | 0x60000000 (Fixed) |
Unit 0 Chip Select 0 End Address | 0x63FFFFFF (64MB Size) | 0x63FFFFFF (64MB Size) |
Unit 0 Chip Select 1 Start Address | 0x64000000 (Fixed) | 0x64000000 (Fixed) |
Unit 0 Chip Select 1 End Address | 0x640FFFFF (default) | 0x640FFFFF (default) |
Unit 1 Chip Select 0 Start Address | 0x68000000 (Fixed) | 0x68000000 (Fixed) |
Unit 1 Chip Select 0 End Address | 0x680FFFFF (default) | 0x680FFFFF (default) |
Unit 1 Chip Select 1 Start Address | 0x6C000000 (Fixed) | 0x6C000000 (Fixed) |
Unit 1 Chip Select 1 End Address | 0x6C0FFFFF (default) | 0x6C0FFFFF (default) |
Auto-calibration procedure is triggered automatically when the 'Data latching delay' field in the configurator properties is set to 0. The user application is responsible for setting the appropriate preamble pattern before calling R_XSPI_OSPI_Open() with 8D-8D-8D(OPI) mode or changing the SPI protocol to 8D-8D-8D(OPI) using R_XSPI_OSPI_SpiProtocolSet() API. The appropriate preamble pattern can be written to the desired address using the R_XSPI_OSPI_Write() API while in the 1S-1S-1S(SPI) mode. Ensure that the same address is passed through the configurator. If the OctaFlash chip is already in 8D-8D-8D(OPI) mode, the preamble pattern must be programmed using the debugger before calling R_XSPI_OSPI_Open().
Chip select latencies can be set through the configurator. The default settings support 1S-1S-1S(SPI) at minimum latency. In case the driver is opened in 1S-1S-1S(SPI) mode and will be switched to 8D-8D-8D(OPI) mode later using R_XSPI_OSPI_SpiProtocolSet(), please select latencies required for 8D-8D-8D(OPI) before calling R_XSPI_OSPI_Open().
When using the IAR compiler, OSPI data must be const
qualified to be downloaded by the debugger.
This is a basic example of minimal use of the OSPI in an application. When using the section definition in the example below, the user must define it separately in the linker configuration file.
This is an example of using R_XSPI_OSPI_DirectTransfer with write direction followed by R_XSPI_OSPI_DirectTransfer with read direction to send the write enable command and read back the status register from the device.
This is an example of using R_XSPI_OSPI_SpiProtocolSet to change the operating mode from 1S-1S-1S(SPI) to 8D-8D-8D(OPI) and the specific configuration procedure for OctaFlash.
This is an example of using R_XSPI_OSPI_SpiProtocolSet to change the operating mode from 1S-1S-1S(SPI) to 8D-8D-8D(OPI) and allow the driver to initiate auto-calibration.
This is an example of using R_CGC_SystemClockSet to change the Octal-SPI clock frequency during run time. The xSPI_CLK frequency must be updated before calling the R_XSPI_OSPI_SpiProtocolSet with appropriate clock source and divider settings required to be set for the new SPI protocol mode. Ensure that the clock source selected is started.
This is an example of using R_XSPI_OSPI_Write() to write a page of data to memory space for RZ/T2M and RZ/T2L. In these MCU environments, R_XSPI_OSPI_Write() attempts memory mapping accesses. In this case, the memory access attribute of the External Address Space xSPIn should be device-nGnRnE, because write access to flash memory needs to be in the right order. Therefore, R_BSP_MpuRegionDynamicConfig() and R_BSP_MpuRegionRestoreConfig() are used to temporarily change the memory access attribute.
This is an example of using R_XSPI_OSPI_DirectTransfer() to write a page of data to memory space. If two memories are connected on the same unit's xSPI bus, memory mapping write may not be possible due to bus collisions caused by simultaneous accesses to the xSPI area. In this case, it is recommended to write data using R_XSPI_OSPI_DirectTransfer() instead of R_XSPI_OSPI_Write().
Data Structures | |
struct | xspi_ospi_instance_ctrl_t |
Enumerations | |
enum | xspi_ospi_chip_select_t |
enum | xspi_ospi_memory_size_t |
enum | xspi_ospi_command_interval_clocks_t |
enum | xspi_ospi_cs_pullup_clocks_t |
enum | xspi_ospi_cs_pulldown_clocks_t |
enum | xspi_ospi_prefetch_function_t |
enum | xspi_ospi_io_voltage_t |
enum | xspi_ospi_byte_order_t |
struct xspi_ospi_instance_ctrl_t |
Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called
fsp_err_t R_XSPI_OSPI_Open | ( | spi_flash_ctrl_t * | p_ctrl, |
spi_flash_cfg_t const *const | p_cfg | ||
) |
Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory.
Implements spi_flash_api_t::open.
FSP_SUCCESS | Configuration was successful. |
FSP_ERR_ASSERTION | The parameter p_ctrl or p_cfg is NULL. |
FSP_ERR_ALREADY_OPEN | Driver has already been opened with the same p_ctrl. |
FSP_ERR_CALIBRATE_FAILED | Failed to perform auto-calibrate. |
fsp_err_t R_XSPI_OSPI_Close | ( | spi_flash_ctrl_t * | p_ctrl | ) |
Close the OSPI driver module.
Implements spi_flash_api_t::close.
FSP_SUCCESS | Configuration was successful. |
FSP_ERR_ASSERTION | p_instance_ctrl is NULL. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
fsp_err_t R_XSPI_OSPI_DirectWrite | ( | spi_flash_ctrl_t * | p_ctrl, |
uint8_t const *const | p_src, | ||
uint32_t const | bytes, | ||
bool const | read_after_write | ||
) |
Writes raw data directly to the OctaFlash. API not supported. Use R_XSPI_OSPI_DirectTransfer
Implements spi_flash_api_t::directWrite.
FSP_ERR_UNSUPPORTED | API not supported by OSPI. |
fsp_err_t R_XSPI_OSPI_DirectRead | ( | spi_flash_ctrl_t * | p_ctrl, |
uint8_t *const | p_dest, | ||
uint32_t const | bytes | ||
) |
Reads raw data directly from the OctaFlash. API not supported. Use R_XSPI_OSPI_DirectTransfer.
Implements spi_flash_api_t::directRead.
FSP_ERR_UNSUPPORTED | API not supported by OSPI. |
fsp_err_t R_XSPI_OSPI_SpiProtocolSet | ( | spi_flash_ctrl_t * | p_ctrl, |
spi_flash_protocol_t | spi_protocol | ||
) |
Sets the SPI protocol.
Implements spi_flash_api_t::spiProtocolSet.
FSP_SUCCESS | SPI protocol updated on MPU peripheral. |
FSP_ERR_ASSERTION | A required pointer is NULL. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
FSP_ERR_CALIBRATE_FAILED | Failed to perform auto-calibrate. |
fsp_err_t R_XSPI_OSPI_XipEnter | ( | spi_flash_ctrl_t * | p_ctrl | ) |
Enters XIP (execute in place) mode.
Implements spi_flash_api_t::xipEnter.
FSP_ERR_UNSUPPORTED | API not supported by OSPI. |
fsp_err_t R_XSPI_OSPI_XipExit | ( | spi_flash_ctrl_t * | p_ctrl | ) |
Exits XIP (execute in place) mode.
Implements spi_flash_api_t::xipExit.
FSP_ERR_UNSUPPORTED | API not supported by OSPI. |
fsp_err_t R_XSPI_OSPI_Write | ( | spi_flash_ctrl_t * | p_ctrl, |
uint8_t const *const | p_src, | ||
uint8_t *const | p_dest, | ||
uint32_t | byte_count | ||
) |
Program a page of data to the flash.
Implements spi_flash_api_t::write.
FSP_SUCCESS | The flash was programmed successfully. |
FSP_ERR_ASSERTION | p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
FSP_ERR_DEVICE_BUSY | Another Write/Erase transaction is in progress. |
FSP_ERR_WRITE_FAILED | Write operation failed. |
fsp_err_t R_XSPI_OSPI_Erase | ( | spi_flash_ctrl_t * | p_ctrl, |
uint8_t *const | p_device_address, | ||
uint32_t | byte_count | ||
) |
Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.
Implements spi_flash_api_t::erase.
FSP_SUCCESS | The command to erase the flash was executed successfully. |
FSP_ERR_ASSERTION | p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase size defined in spi_flash_cfg_t, or byte_count is set to 0. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
FSP_ERR_DEVICE_BUSY | The device is busy. |
FSP_ERR_WRITE_FAILED | Write operation failed. |
fsp_err_t R_XSPI_OSPI_StatusGet | ( | spi_flash_ctrl_t * | p_ctrl, |
spi_flash_status_t *const | p_status | ||
) |
Gets the write or erase status of the flash.
Implements spi_flash_api_t::statusGet.
FSP_SUCCESS | The write status is in p_status. |
FSP_ERR_ASSERTION | p_instance_ctrl or p_status is NULL. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
fsp_err_t R_XSPI_OSPI_BankSet | ( | spi_flash_ctrl_t * | p_ctrl, |
uint32_t | bank | ||
) |
Selects the bank to access.
Implements spi_flash_api_t::bankSet.
FSP_ERR_UNSUPPORTED | API not supported by OSPI. |
fsp_err_t R_XSPI_OSPI_DirectTransfer | ( | spi_flash_ctrl_t * | p_ctrl, |
spi_flash_direct_transfer_t *const | p_transfer, | ||
spi_flash_direct_transfer_dir_t | direction | ||
) |
Read/Write raw data directly with the OctaFlash.
Implements spi_flash_api_t::directTransfer.
FSP_SUCCESS | The flash was programmed successfully. |
FSP_ERR_ASSERTION | A required pointer is NULL. |
FSP_ERR_NOT_OPEN | Driver is not opened. |
fsp_err_t R_XSPI_OSPI_AutoCalibrate | ( | spi_flash_ctrl_t * | p_ctrl | ) |
Auto-calibrate the OctaRAM device using the preamble pattern. Unsupported by XSPI_OSPI.
Implements spi_flash_api_t::autoCalibrate.
FSP_ERR_UNSUPPORTED | API not supported by XSPI_OSPI |